EPC2TI32N - 1.6Mb ISP Configuration PROM for FPGA | Altera / Intel
MPN: EPC2TI32N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
EPC2TI32N Overview
What is a configuration PROM? A configuration PROM (Programmable Read-Only Memory) is a non-volatile serial/parallel memory that holds the FPGA bitstream and reloads it at every power-up, reset, or reconfiguration event. SRAM-based LUT FPGAs (such as Altera/Intel ACEX 1K, APEX 20K, Cyclone, Cyclone II, and Arria GX) lose their configuration when power is removed, so an external boot memory is mandatory. Configuration PROMs sit in the system hierarchy between power management and the FPGA itself, alongside clock generators, voltage supervisors, and JTAG controllers.
Key features include 1.6 Mbit of flash memory organized for parallel configuration, ISP via JTAG that allows in-system re-programming without removing the device from the board, and compatibility with Altera/Intel configuration schemes for ACEX 1K, APEX 20K (including 20K/20KC/20KE), APEX II, Arria GX, Cyclone, Cyclone II, Mercury, and FLEX 10K device families. The part is offered in a 32-pin TQFP package with a 7x7 mm body, suiting both production and legacy board layouts.
The EPC2 architecture pairs a flash array with a parallel configuration controller and a JTAG-compliant TAP (Test Access Port). On power-up, the device automatically serializes/parallelizes the stored bitstream out to the FPGA via dedicated configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA). Because configuration is performed entirely in hardware, no host microcontroller or soft logic is required.
Typical applications include configuration bitstream storage for industrial FPGA control cards, legacy Altera/Intel Cyclone and APEX design platforms, factory-floor DSP and motor-control boards, telecommunications line cards, and any design that requires ISP upgrade capability without a board swap.
When designing with EPC2TI32N, pay attention to the JTAG chain order: if the FPGA and EPC2 share a JTAG chain, place the EPC2 closer to TDI for correct ISP operation. Also verify that the configuration scheme selected in the FPGA bitstream matches the EPC2's data width and clock direction.
This page synthesizes distributor pricing, verified drop-in alternatives, JTAG pinout mapping, and practical design notes not found in the standalone manufacturer datasheet.
Drop-in alternatives for EPC2TI32N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC2TI32N (same form factor and footprint) β differing in Memory Type, Interface, Package, Operating Temperature, Supply Voltage.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC2TC32N
β Drop-Inβ In Stock
$9.2 / Unit
View Datasheet βEPC2TI32
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC144TI32N
β Drop-Inπ Reference alternative (not in catalog)
EPC1TI32
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPC1TI32N
β Drop-Inπ Reference alternative (not in catalog)
EPC2TI32N Maximum Ratings & Electrical Characteristics
| Memory Type | In-System Programmable Configuration PROM (Flash) |
| Memory Size | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) |
| Interface Type | Parallel configuration data output + JTAG (IEEE 1149.1) ISP |
| Supply Voltage - 3.3V Mode | 3.0 V to 3.6 V |
| Supply Voltage - 5V Mode | 4.5 V to 5.5 V |
| Operating Temperature | -40C to +85C |
| Package / Case | 32-TQFP (7x7 mm) |
| Mounting Type | Surface Mount |
| Packaging | Tray |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, Mercury, FLEX 10K |
| JTAG Interface | Yes (IEEE 1149.1 compliant TAP for ISP) |
| Configuration Pins | nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[7:0] |
EPC2TI32N Pin Configuration
| Pin 1 | DATA0 β Configuration data output bit 0 |
| Pin 2 | DATA1 β Configuration data output bit 1 |
| Pin 3 | DATA2 β Configuration data output bit 2 |
| Pin 4 | DATA3 β Configuration data output bit 3 |
| Pin 5 | DATA4 β Configuration data output bit 4 |
| Pin 6 | DATA5 β Configuration data output bit 5 |
| Pin 7 | DATA6 β Configuration data output bit 6 |
| Pin 8 | DATA7 β Configuration data output bit 7 |
| Pin 9 | nCS β Chip select (active low) |
| Pin 10 | nCONFIG β Configuration control input (active low) |
| Pin 11 | nSTATUS β Status output (active low) |
| Pin 12 | CONF_DONE β Configuration done indicator |
| Pin 13 | DCLK β Configuration clock output |
| Pin 14 | OE β Output enable |
| Pin 15 | VCC β Supply voltage (3.3 V or 5 V) |
| Pin 16 | GND β Ground |
| Pin 17 | TDI β JTAG Test Data In |
| Pin 18 | TDO β JTAG Test Data Out |
| Pin 19 | TMS β JTAG Test Mode Select |
| Pin 20 | TCK β JTAG Test Clock |
| Pin 21 | GND β Ground |
| Pin 22 | VCC β Supply voltage |
| Pin 23 | NC β Not connected (per datasheet) |
| Pin 24 | NC β Not connected (per datasheet) |
| Pin 25 | GND β Ground |
| Pin 26 | NC β Not connected (per datasheet) |
| Pin 27 | NC β Not connected (per datasheet) |
| Pin 28 | NC β Not connected (per datasheet) |
| Pin 29 | GND β Ground |
| Pin 30 | NC β Not connected (per datasheet) |
| Pin 31 | NC β Not connected (per datasheet) |
| Pin 32 | NC β Not connected (per datasheet) |
Typical Applications
EPC2TI32N is suitable for 6 applications: APEX 20K FPGA Configuration Storage, Cyclone / Cyclone II FPGA Boot Memory, Arria GX Telecom Line Card Configuration, Factory Automation Motor Controller, Mercury FPGA DSP Board Boot Memory, Legacy APEX II System Controller.
APEX 20K FPGA Configuration Storage
The EPC2TI32N's 1.6 Mbit flash capacity aligns with APEX 20K, 20KC, and 20KE bitstream densities, making it a drop-in boot memory for industrial APEX designs. Its JTAG ISP interface allows field firmware upgrades without desoldering, which is critical for installed industrial control systems. The 32-TQFP footprint is shared across the APEX 20K evaluation board reference designs, easing layout reuse and revision control for long-lifecycle equipment.
Recommended
Cyclone / Cyclone II FPGA Boot Memory
The EPC2TI32N configures Altera Cyclone and Cyclone II devices through the parallel configuration interface, providing a non-volatile store for the FPGA bitstream at every power-up. The 1.6 Mbit density covers typical Cyclone designs including NIOS II soft-core firmware overlays, and the dual 3.3 V / 5 V supply simplifies integration with both legacy and modern boards. Industrial -40C to +85C rating supports factory floor deployment.
Recommended
Arria GX Telecom Line Card Configuration
In telecommunications line cards based on Arria GX FPGAs, the EPC2TI32N provides reliable non-volatile boot storage with parallel configuration bandwidth, allowing fast FPGA bring-up at line-card insertion. The JTAG ISP interface enables remote firmware updates during service windows, and the industrial temperature range suits central-office and outdoor-cabinet environments. The dual-voltage supply (3.3 V or 5 V) matches typical telecom backplane rails.
Recommended
Factory Automation Motor Controller
Motor controller boards based on ACEX 1K or FLEX 10K FPGAs benefit from the EPC2TI32N's industrial -40C to +85C operation and JTAG-driven field re-programming for tuning control loops without removing the card from the machine. The 1.6 Mbit density accommodates DSP firmware blocks for vector control and encoder processing. The 32-TQFP 7x7 mm package suits the compact form factors typical of industrial servo drives.
Recommended
Mercury FPGA DSP Board Boot Memory
The Altera Mercury device family pairs naturally with the EPC2TI32N for high-speed DSP applications including software-defined radio and baseband processing. The parallel configuration interface delivers fast load times for dense Mercury bitstreams, while JTAG ISP enables laboratory and field firmware iteration. Dual 3.3 V / 5 V supply operation simplifies integration with existing Mercury reference designs.
Recommended
Legacy APEX II System Controller
The APEX II FPGA family requires non-volatile boot storage at every power-up, and the EPC2TI32N's 1.6 Mbit density covers typical APEX II bitstreams including embedded processor cores. Its JTAG ISP interface supports in-system updates for long-lifecycle APEX II systems in transportation, energy, and defense applications. The 32-TQFP package is footprint-compatible with earlier APEX II reference designs, minimizing migration effort.
Recommended
Recommended Products Summary
Engineering reference data for EPC2TI32N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2TC32N | EPC2TI32 | EPC144TI32N | EPC1TI32 | EPC1TI32N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) | Altera (Intel FPGA) |
| Package | 32-TQFP (7x7 mm) | 32-TQFP (7x7 mm) - same | 32-TQFP (7x7 mm) - same | 32-TQFP (7x7 mm) - same | 32-TQFP (7x7 mm) - same | 32-TQFP (7x7 mm) - same |
| Memory Size | 1.6 Mbit | 1.6 Mbit | 1.6 Mbit | Lower density (EPC144 family) | Lower density (EPC1 family) | Lower density (EPC1 family) |
| Supply Voltage | 3.0-3.6 V or 4.5-5.5 V | 3.0-3.6 V or 4.5-5.5 V | 3.0-3.6 V or 4.5-5.5 V | 3.0-3.6 V or 4.5-5.5 V | 3.0-3.6 V or 4.5-5.5 V | 3.0-3.6 V or 4.5-5.5 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Configuration Interface | Parallel (8-bit DATA + DCLK) | Parallel (8-bit DATA + DCLK) | Parallel (8-bit DATA + DCLK) | Parallel (EPC144 family) | Parallel (EPC1 family) | Parallel (EPC1 family) |
Key Differentiators
- Industrial -40C to +85C operating temperature (N-suffix variant) (vs EPC2TI32)
- Higher density than EPC1 / EPC144 family members (vs EPC1TI32N, EPC144TI32N)
- Parallel configuration interface vs EPCS serial devices (vs EPCS16)
Design Notes
When migrating between EPC2 family members (EPC2TI32N to EPC2TC32N, EPC144TI32N, or EPC1 family), verify the bitstream density fit: EPC2 = 1.6 Mbit, EPC144 family has lower density, EPC1 family has even lower density. An undersized PROM will truncate the FPGA configuration and CONF_DONE will not assert. Always regenerate the bitstream and check the .rbf size before substituting.
Place the EPC2TI32N close to the FPGA's configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[7:0]) and route DATA lines as parallel-matched traces of equal length. JTAG signals (TDI, TDO, TMS, TCK) should be routed to the JTAG header with stubs shorter than 10 mm to preserve signal integrity at typical TCK frequencies up to 33 MHz. Decouple VCC with a 0.1 uF ceramic capacitor placed within 5 mm of each VCC pin.
If the EPC2TI32N shares the JTAG chain with the FPGA, place the EPC2 closer to TDI (Test Data In) than the FPGA. This ordering is mandatory for Altera/Intel ISP flow - if the FPGA is closer to TDI, the JTAG chain can still be programmed but ISP-to-EPC2 may fail with chain integrity errors. Always include a JTAG chain tester in your bring-up flow.
Compliance Information
RoHS and lead-free status not explicitly stated in the verified data. The N-suffix suggests lead-free per Altera's legacy naming convention, but this cannot be confirmed without explicit datasheet statement. Marked as [DATA_NEEDED] in specs. Part is listed as obsolete by multiple distributors.
