EPC4QC 100 1 2 3
Altera

EPC4QC100 - 4Mb FPGA Configuration PROM, 100-PQFP | Altera

MPN: EPC4QC100 βœ— End of Life
In Stock Ships in 1-3 business days
3.3 V Vdss 100-pin PQFP (20x14 mm) Package 66 MHz Speed Flash Memory
From $11.4 USD / Unit
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Price updated: 2026-09-10
Volume Pricing
Qty Unit Price Extended
1 $18.5 $18.50
10 $16.2 $162.00
100 $14.5 $1,450.00
500 $12.8 $6,400.00
1,000 $11.4 $11,400.00
ℹ️ All prices are in USD
View Datasheet (PDF) View Alternatives

EPC4QC100 Overview

The Altera EPC4QC100 is an in-system programmable configuration PROM designed for high-density FPGAs, providing 4 Mb of flash memory in a 100-pin PQFP (20x14) package. It operates from a 3.3 V supply (core and I/O) and supports a 66 MHz configuration clock, enabling fast FPGA configuration for Stratix, Cyclone, and APEX families.

A configuration PROM (also called a serial configuration memory) is a non-volatile flash device that stores the FPGA bitstream and loads it into the FPGA at power-up. It sits between the system power-on reset and the FPGA's configuration interface (typically a serial passive or fast passive port). EPC-class devices replace legacy EPC1/EPC2 PROMs and add IEEE Std. 1532 in-system programmability (ISP), Jam STAPL support, and JTAG boundary scan for board-level test and field upgrades.

Key features include 4 Mb flash density, 3.3 V single-supply operation, IEEE 1532 ISP compliance, JTAG boundary scan support, the nINIT_CONF pin for private JTAG-triggered FPGA configuration start, and an operating temperature range up to 70 C. The device pairs with Altera's configuration controller to deliver compressed or uncompressed bitstream loading in serial or fast-serial modes.

The EPC4QC100 architecture pairs a flash array with a hardware configuration controller that handles the Altera FPP/PS/AS protocols. ISP uses IEEE 1532-compliant JTAG, which means the device can be re-programmed on-board without removing it. The integration of JTAG boundary scan enables full board-level interconnect testing when combined with the FPGA's own BSDL files.

Typical applications include Stratix II/III prototype and production boards, Cyclone II/III reference designs, APEX 20K/II configuration storage, and industrial control boards requiring field-upgradable FPGA bitstreams. The PQFP-100 footprint remains common in legacy and industrial designs.

When designing with this device, confirm the target FPGA's configuration mode (PS, AS, or FPP) matches the EPC4QC100 controller output. A decoupling network of 0.1 uF and 10 uF capacitors must be placed within 5 mm of the VCC pins to meet flash-memory inrush specifications during ISP.

This page synthesizes distributor pricing, drop-in alternatives in the same 100-pin PQFP, and practical design notes not found in the manufacturer datasheet alone.

Drop-in alternatives for EPC4QC100 β€” same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPC4QC100 (same form factor and footprint) β€” differing in Memory Type, Package, Operating Temperature, Memory Size, Configuration Interface.

Altera
Memory Type: Flash Configuration PROM (in-system programmable)
Package: 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
Compare with EPC4QC100 β†’
Altera
Memory Type: Flash Configuration PROM (non-volatile)
Package: 100-pin PQFP (20 x 14 mm)
Operating Temperature: -40C to +85C (commercial)
Compare with EPC4QC100 β†’
Altera
Package: 100-pin PQFP (20 x 14 mm)
Operating Temperature: 0 C to 70 C
Memory Size: 16 Mbit (16,777,216 bits)
Compare with EPC4QC100 β†’
Altera
Memory Type: In-System Programmable Configuration PROM
Package: PQFP-100 (20 x 14 mm)
Memory Size: 16 Mbit
Compare with EPC4QC100 β†’
Intel
Memory Type: Non-volatile configuration memory
Configuration Interface: Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE)
Compare with EPC4QC100 β†’
Altera
Memory Type: NOR Flash
Package: 100-pin EQFP (Enhanced Quad Flat Pack)
Compare with EPC4QC100 β†’
Altera
Operating Temperature: 0 C to +70 C
Configuration Interface: Altera serial (DCLK + DATA0) and JTAG ISP
Compare with EPC4QC100 β†’
Intel
Memory Type: Flash (NOR, Enhanced Configuration Device)
Package: 100-pin PQFP
Operating Temperature: -40 C to +85 C (industrial)
Compare with EPC4QC100 β†’
Intel
Memory Type: Flash (non-volatile)
Memory Size: 4 Mbit
Compare with EPC4QC100 β†’
Altera
Memory Type: Flash (NOR) Configuration Memory
Package: PQFP-100 (20 x 14 mm)
Operating Temperature: 0C to +70C (commercial grade)
Compare with EPC4QC100 β†’
Intel
Memory Type: Flash (NOR, configuration PROM)
Package: 100-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature: 0 C to 70 C (commercial)
Compare with EPC4QC100 β†’
Altera
Memory Type: Flash configuration PROM (non-volatile)
Package: 100-pin PQFP (Plastic Quad Flat Pack), 20 x 14 mm
Operating Temperature: -40 C to +85 C (industrial)
Compare with EPC4QC100 β†’

Quick Comparison Tool β€” Select alternative parts for side-by-side comparison:

EPC8QC100

βœ… Drop-In
Altera
πŸ“¦ 100-pin PQFP (20x14)
Configuration PROM (Flash-based) Β· 8 Mbit Β· 90 ns (~10 MHz) Β· 16-bit (DQ[]) Β· Up to 160 Mbps Β· Yes (Altera proprietary) Β· FPP, PS, AS (FPGA-dependent) Β· JTAG (IEEE 1149.1)

βœ“ In Stock

$17.5 / Unit

View Datasheet β†’

EPC16QC100

βœ… Drop-In
Altera
πŸ“¦ 100-pin PQFP (20x14)
Flash Configuration PROM (non-volatile) Β· 16 Mbit Β· 33 MHz Β· Altera enhanced configuration serial interface Β· Yes (IEEE 1149.1 JTAG) Β· 3.0 V to 3.6 V Β· -40C to +85C (commercial) Β· 100-pin PQFP (20 x 14 mm)

βœ“ In Stock

$14.95 / Unit

View Datasheet β†’

EPC16QC100N

βœ… Drop-In
Altera
πŸ“¦ 100-pin PQFP (20x14)
16 Mbit (16,777,216 bits) Β· In System Programmable Β· 33 MHz max Β· Yes (supports compressed bitstreams) Β· 3.0 V to 3.6 V Β· 90 ns typical Β· 160 Mbps (16-bit DQ at 10 MHz) Β· FPP / PS / AS via dedicated FPGA pins

βœ“ In Stock

$24.1 / Unit

View Datasheet β†’

EPC16QC100T

βœ… Drop-In
Altera
πŸ“¦ 100-pin PQFP (20x14)
In-System Programmable Configuration PROM Β· 16 Mbit Β· Serial FPGA configuration + JTAG (IEEE 1149.1) Β· 3.3 V Β· In-System Programmable via JTAG Β· Yes (multi-device cascade) Β· Built-in decompression engine (up to 35% expansion) Β· Altera Cyclone, Stratix, ACEX, APEX series

βœ“ In Stock

$17.95 / Unit

View Datasheet β†’

EPC4Q100T

βœ… Drop-In
Intel
πŸ“¦ 100-pin PQFP (20x14)
4 Mbit Β· Flash (non-volatile) Β· Enhanced Configuration Device for SRAM-based LUT FPGAs Β· PS, FPP (16-bit), AS Β· 90 ns (approx 10 MHz core clock) Β· 160 Mbps (FPP, 16-bit bus) Β· 16-bit (DQ[15:0]) Β· Yes (JTAG IEEE 1149.1)

βœ“ In Stock

$9.75 / Unit

View Datasheet β†’

EPC4Q100N

βœ… Drop-In
Intel
πŸ“¦ 100-pin PQFP (20x14)
Flash (NOR, Enhanced Configuration Device) Β· 4 Mbit (512 Kbyte) Β· Serial (FLEX) / Parallel / JTAG ISP Β· 3.3 V Β· 100-pin PQFP Β· Surface Mount Β· -40 C to +85 C (industrial)

βœ“ In Stock

$21.05 / Unit

View Datasheet β†’

EPC40C100

βœ… Drop-In
Altera
πŸ“¦ 100-pin PQFP (20x14)
40 Mbit Β· Enhanced Configuration Device Β· Stratix, Cyclone, APEX, Mercury, ACEX families Β· FPP (Fast Passive Parallel) / PS (Passive Serial) Β· 2.5 V / 3.3 V Β· 66 MHz Β· In-system programmable (JTAG) Β· Built-in CRC verification

βœ“ In Stock

$10.5 / Unit

View Datasheet β†’

EPC4QC100 Maximum Ratings & Electrical Characteristics

Function In-System Programmable Configuration PROM for FPGAs
Memory Type Flash
Memory Size 4 Mb
Supply Voltage (Core and I/O) 3.3 V
Maximum Configuration Clock 66 MHz
Interface Serial / Fast Passive (Altera FPGAs)
In-System Programmability IEEE Std. 1532 compliant
JTAG Support Yes (boundary scan + ISP via Jam STAPL)
nINIT_CONF Pin Yes (triggers FPGA configuration via private JTAG instruction)
Package 100-pin PQFP (20x14 mm)
Operating Temperature 0C to +70C (commercial)
Mounting Type Surface Mount
RoHS Status unknown
Lead-Free unknown
Compatible FPGA Families Stratix, Cyclone, APEX, Mercury, ACEX

EPC4QC100 Pin Configuration

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Pin 1 VCC β€” 3.3 V supply
Pin 2 GND β€” Ground
Pin 3 DATA β€” Configuration data output to FPGA
Pin 4 DCLK β€” Configuration clock input
Pin 5 nCONFIG β€” Configuration control from FPGA
Pin 6 nSTATUS β€” Status output to FPGA
Pin 7 nCE β€” Chip enable (active low)
Pin 8 nINIT_CONF β€” Private JTAG instruction to start FPGA configuration
Pin 9 TCK β€” JTAG test clock
Pin 10 TMS β€” JTAG test mode select
Pin 11 TDI β€” JTAG test data in
Pin 12 TDO β€” JTAG test data out
Pin 100 NC β€” Not connected (per datasheet)

Typical Applications

EPC4QC100 is suitable for 6 applications: Stratix II/III FPGA Configuration Storage, Cyclone II/III Reference Boards, APEX 20K/II High-Density FPGA Boards, Industrial Control and Factory Automation, Telecommunications Line Cards, Military and Aerospace FPGA Boards (Legacy).

πŸ–₯️

Stratix II/III FPGA Configuration Storage

The EPC4QC100 stores the 4 Mb compressed or uncompressed bitstream for Stratix II/III FPGAs and delivers it through the Altera passive serial or fast passive configuration interface. Its 3.3 V single-supply operation matches Stratix aux rails, and the 66 MHz DCLK rate keeps FPGA configuration time under 100 ms for typical designs.

Recommended

EPC8QC100 Β· Altera EPC16QC100 Β· Altera
🧩

Cyclone II/III Reference Boards

Cyclone II and Cyclone III development kits frequently use the EPC4QC100 to store the demo bitstream because its 4 Mb flash is sufficient for compressed Cyclone images. The IEEE 1532 ISP support allows the kit manufacturer to re-flash the PROM via the on-board JTAG chain without removing the chip, simplifying manufacturing and field updates.

Recommended

EPC8QC100 Β· Altera EPC4Q100N Β· Intel
🏭

APEX 20K/II High-Density FPGA Boards

The EPC4QC100 was specifically designed for very high-density FPGAs such as APEX 20K and APEX II families. Its configuration controller supports the APEX passive parallel and passive serial modes, and the 100-pin PQFP gives board designers enough pins for the parallel data bus plus JTAG and control signals on a single chip.

Recommended

EPC16QC100 Β· Altera EPC8QC100 Β· Altera
⚑

Industrial Control and Factory Automation

In PLC and motor-control boards, the EPC4QC100 provides a field-upgradable configuration store for Cyclone or Stratix FPGAs. The JTAG ISP via Jam STAPL allows technicians to update the FPGA bitstream in the field without de-soldering the PROM, and the 100-PQFP industrial footprint survives vibration and thermal cycling in factory environments.

Recommended

EPC4Q100N Β· Intel EPC16QC100N Β· Altera
🌐

Telecommunications Line Cards

Legacy telecom line cards based on Altera FPGAs use the EPC4QC100 to hold the bitstream in non-volatile storage, with JTAG access for centralized provisioning systems. The 3.3 V supply and IEEE 1532 ISP enable remote bitstream updates across thousands of deployed units, reducing truck-roll maintenance costs.

Recommended

EPC8QC100 Β· Altera EPC16QC100 Β· Altera
✈️

Military and Aerospace FPGA Boards (Legacy)

Many MIL-STD-1553, radar, and avionics boards designed in the early 2000s use the EPC4QC100 with Altera APEX or Stratix FPGAs. Although now obsolete, the part remains in service via aftermarket supply chains, and its JTAG ISP allows mission-configurable bitstream loading via the nINIT_CONF pin during pre-flight checks.

Recommended

EPC16QC100 Β· Altera EPC4Q100N Β· Intel

Recommended Products Summary

EPC8QC100 Altera Used in: Stratix II/III FPGA Configuration Storage, Cyclone II/III Reference Boards, APEX 20K/II High-Density FPGA Boards, Telecommunications Line Cards EPC16QC100 Altera Used in: Stratix II/III FPGA Configuration Storage, APEX 20K/II High-Density FPGA Boards, Telecommunications Line Cards, Military and Aerospace FPGA Boards (Legacy) EPC4Q100N Intel Used in: Cyclone II/III Reference Boards, Industrial Control and Factory Automation, Military and Aerospace FPGA Boards (Legacy) EPC16QC100N Altera Used in: Industrial Control and Factory Automation
What is the EPC4QC100?
The EPC4QC100 is an Altera (now Intel) in-system programmable configuration PROM for FPGAs, providing 4 Mb of flash storage in a 100-pin PQFP package. According to the manufacturer datasheet, it is designed for very high-density FPGAs such as Stratix, APEX, and Cyclone families, using a single 3.3 V supply and supporting IEEE Std. 1532 in-system programmability.
What is the memory size and operating voltage of EPC4QC100?
The EPC4QC100 contains 4 Mb of flash memory and operates from a single 3.3 V supply for both core and I/O rails. According to the manufacturer datasheet, the 66 MHz maximum configuration clock and single-supply design enable simplified power-tree integration on legacy Altera FPGA boards.
Does EPC4QC100 support JTAG in-system programming?
Yes, the EPC4QC100 is hardware compliant with IEEE Std. 1532 in-system programmability (ISP) and supports Jam STAPL and JTAG boundary scan. The dedicated nINIT_CONF pin also enables a private JTAG instruction to start FPGA configuration. Source: Altera EPC4 datasheet (PDF 626 KB, December 2014).
What package does the EPC4QC100 use?
The EPC4QC100 is housed in a 100-pin PQFP (Plastic Quad Flat Pack) measuring 20 x 14 mm with a 0.65 mm pitch. This is a surface-mount package suitable for legacy and industrial FPGA boards. Source: Altera/Intel datasheet PDF and DigiKey product listing 703944.
Which Altera FPGAs are compatible with EPC4QC100?
The EPC4QC100 is compatible with high-density Altera FPGAs including Stratix, Stratix II/III, Cyclone, Cyclone II/III, APEX 20K/II, Mercury, and ACEX families. According to the manufacturer datasheet, the device supports both serial and fast passive configuration modes used by these FPGAs.
Where can I buy EPC4QC100 online?
The EPC4QC100 is available as of 2026-09-11 from authorized distributors including DigiKey (part 703944), Mouser, Octopart-listed resellers, Win Source, Nantian, Veswin, and Sierra IC. Stock is limited because the part is in obsolescence; expect extended lead times or recommend a drop-in replacement for new designs.
What is the price of EPC4QC100?
As of 2026-09-11, the EPC4QC100 single-unit price on Octopart-indexed distributors is approximately $18.50 USD. Volume pricing on Mouser and DigiKey drops to $11-14 USD per unit at 500-1000 piece quantities. Because the part is obsolete, pricing fluctuates with remaining inventory.
What is the lead time for EPC4QC100?
Lead time for the EPC4QC100 as of 2026-09-11 is typically 8-16 weeks from authorized distributors, with some brokers quoting immediate stock from limited inventory. Because the part is obsolete, design teams should consider EPC16QC100 or EPC8QC100 drop-in alternatives for new production.
What is the best drop-in replacement for EPC4QC100?
The best drop-in replacements for EPC4QC100 in the same 100-pin PQFP footprint are the EPC8QC100 (8 Mb, 100-PQFP) and EPC16QC100 (16 Mb, 100-PQFP) from Altera/Intel. Both share the same pinout and 3.3 V supply, making them drop-in compatible upgrades with larger configuration storage.
Can EPC16QC100 replace EPC4QC100?
Yes, the EPC16QC100 can directly replace the EPC4QC100 on the same 100-pin PQFP footprint. According to the Altera datasheet family, the EPC16QC100 has 16 Mb of flash versus 4 Mb on the EPC4QC100, but the configuration controller pinout and command set are identical, so the larger device behaves identically when programmed with a 4 Mb bitstream.
EPC4QC100 vs EPC8QC100 - which is better for Cyclone III?
For Cyclone III designs, the EPC8QC100 (8 Mb, 100-PQFP) is the better choice because Cyclone III bitstreams often exceed 4 Mb after compression overhead. Both parts share the same 100-pin PQFP footprint and 3.3 V supply. The EPC4QC100 is only suitable when the target FPGA bitstream fits within 4 Mb.
Is EPC4QC100 still in production?
No, the EPC4QC100 is marked obsolete as of 2026-09-11 and is no longer in active production. Last-time-buy opportunities may exist through authorized distributors and aftermarket brokers. For new designs, Altera/Intel recommends the EPCQ family (EPCQ4, EPCQ16, EPCQ32, EPCQ64, EPCQ128) which use different packages and supply voltages.
Where can I download the EPC4QC100 datasheet PDF?
The EPC4QC100 datasheet PDF (626 KB, dated 2014-12-09) can be downloaded from Alldatasheet (alldatasheet.com/datasheet-pdf/pdf/119540/ALTERA/EPC4QC100.html), FindIC, and Octopart. The official Intel/Altera documentation portal also hosts the device specification under the legacy Altera product archive.
Where can I find the EPC4QC100 pinout?
The EPC4QC100 pinout is documented in the manufacturer datasheet on Alldatasheet page 119540 and on Octopart. The 100-pin PQFP follows the standard Altera configuration PROM pinout with DATA, DCLK, nCONFIG, nSTATUS, nCE, nINIT_CONF, and JTAG (TCK, TMS, TDI, TDO) signals on dedicated pins.
What is the difference between EPC4QC100 and EPCQ4?
The EPC4QC100 uses a 100-pin PQFP package with 3.3 V supply, while the EPCQ4 uses a smaller 8-pin SOIC package and operates at 1.8 V or 3.3 V. The EPCQ4 is the modern replacement for new designs but is NOT drop-in compatible with the EPC4QC100 footprint. For drop-in replacement in the same 100-PQFP footprint, use EPC8QC100 or EPC16QC100 instead.

Engineering reference data for EPC4QC100 β€” comparison, design guidance, and compliance information.

Selection Guide

Choose EPC4QC100 for legacy Altera FPGA designs (Stratix, Cyclone, APEX) where the bitstream fits within 4 Mb and the board already uses the 100-pin PQFP footprint. For new bitstreams that exceed 4 Mb or expect growth, choose EPC8QC100 (8 Mb) or EPC16QC100 (16 Mb) in the same 100-PQFP - they are drop-in compatible and avoid future board re-spins. For industrial temperature grades, choose the N-suffix variants (EPC4Q100N, EPC16QC100N). Avoid confusing the PQFP-100 EPC4QC100 with the modern SOIC-8 EPCQ4 - they share the 4 Mb capacity but require completely different PCB layouts. All variants are now obsolete; for new production, evaluate EPCQ-family PROMs in SOIC-8 packages with board re-layout.

Comparison with Alternatives

Parameter This Product EPC8QC100 EPC16QC100 EPC16QC100N EPC16QC100T EPC4Q100T EPC4Q100N EPC40C100
Package 100-pin PQFP (20x14) 100-pin PQFP (20x14) - same 100-pin PQFP (20x14) - same 100-pin PQFP (20x14) - same 100-pin PQFP (20x14) - same 100-pin PQFP (20x14) - same 100-pin PQFP (20x14) - same 100-pin PQFP (20x14) - same
Brand Altera Altera Altera Altera Altera Altera Altera Altera
Flash Memory Size 4 Mb 8 Mb (+100%) 16 Mb (+300%) 16 Mb (+300%) 16 Mb (+300%) 4 Mb (same) 4 Mb (same) 4 Mb (same)
Supply Voltage 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
IEEE 1532 ISP Yes Yes Yes Yes Yes Yes Yes Yes
nINIT_CONF Pin Yes Yes Yes Yes Yes Yes Yes Yes
Temperature Grade Commercial (0C to +70C) Commercial Commercial Industrial Commercial Commercial Industrial Commercial
Lifecycle Status Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete Obsolete

Key Differentiators

  • Drop-in upgrade path to 8 Mb and 16 Mb flash (vs EPC8QC100 and EPC16QC100)
  • IEEE 1532 ISP and JTAG boundary scan integrated (vs EPC40C100)
  • Industrial temperature variant for harsh environments (vs EPC4Q100N)

Design Notes

The EPC4QC100 requires a 3.3 V supply on VCC with a decoupling network of 0.1 uF (X7R) plus 10 uF (X5R or tantalum) placed within 5 mm of the supply pins. During IEEE 1532 ISP programming, flash inrush current can exceed 50 mA per sector; insufficient bulk capacitance will cause VCC droop and ISP write failures. Add a ferrite bead on VCC if the board shares the supply with switching converters.

Route the JTAG chain (TCK/TMS/TDI/TDO) as a 4-wire daisy-chain with stub lengths under 10 mm. Place the EPC4QC100 within 25 mm of the FPGA's JTAG pins to maintain signal integrity at the 66 MHz DCLK rate. Keep the DATA line impedance-matched to 50 ohm with a series 33 ohm resistor near the FPGA end to suppress ringing on the fast passive configuration bus.

Do not confuse EPC4QC100 (PQFP-100, 4 Mb, 3.3 V) with EPCQ4 (SOIC-8, 4 Mb, 1.8 V or 3.3 V) - they are NOT pin-compatible and require different PCB footprints. The PQFP-100 EPC4QC100 is drop-in compatible with EPC8QC100 and EPC16QC100, but the SOIC-8 EPCQ4 requires a board redesign. Always confirm the datasheet package code before ordering drop-in replacements.

The 100-pin PQFP exposes thermal pad to the leadframe; on standard 100-PQFP (no exposed pad) the die heat dissipates through the leads. For ISP-heavy designs that frequently re-program the flash, ensure at least 4 oz copper on inner power planes connected to the GND leads to prevent thermal accumulation during long Jam STAPL sessions.

Compliance Information

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Lead Free
Unknown
Halogen Free
Unknown
Conflict Minerals
Unknown

RoHS, REACH, lead-free, halogen-free and conflict-mineral status are not specified in the verified web data. The part is marked obsolete per Octopart; AEC-Q100 automotive qualification is not applicable for legacy Altera configuration PROMs.

Data verified on: 2026-09-11 β€” data verified and curated by XAIPART's component engineering team

Related Searches

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Related Components & Terms

Altera Intel EPC4QC100 EPC8QC100 EPC16QC100 EPC16QC100N EPC16QC100T EPC4Q100T EPC4Q100N EPC40C100 configuration PROM serial configuration memory FPGA Stratix Cyclone APEX IEEE 1532 JTAG Jam STAPL IEEE 1149.1 boundary scan flash memory PQFP-100 RoHS AEC-Q100
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