EPC20LC20U - PLCC20 Configuration Device | Altera / Intel FPGA
MPN: EPC20LC20U β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.75 | $157.50 |
| 100 | $12.4 | $1,240.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.2 | $8,200.00 |
EPC20LC20U Overview
A configuration device is a serial-configuration-memory IC that retains the FPGA's configuration bitstream even when the host system is powered down. On power-up, the FPGA's configuration controller reads the bitstream from the EPC over a serial DATA/DCLK chain, eliminating the need for an external boot PROM in many designs. The EPC family sits in the hierarchy: configuration memory -> non-volatile memory -> memory IC -> semiconductor, and is functionally equivalent to a serial PROM dedicated to FPGA configuration protocols.
Key characteristics of EPC20LC20U include a 5.0V tolerant operating supply (per the original Altera EPC2 datasheet that defines the family), a serial configuration interface (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE pins), and compatibility with Altera's proprietary serial configuration protocol. The PLCC-20 (J-lead) package provides mechanical robustness for industrial temperature ranges. In-system programming is supported via Altera's Quartus programmer and the JTAG-style chain, which simplifies board-level bring-up and field firmware updates.
Typical applications include configuring Altera FLEX 10K, FLEX 8000, FLEX 6000, APEX, ACEX, and early Cyclone FPGAs in industrial controllers, telecommunications line cards, military/aerospace retrofits, and legacy prototyping platforms. The 20-pin PLCC package is also convenient for socketed debug environments where the configuration bitstream must be swapped frequently during development.
When designing with EPC20LC20U, verify that the target FPGA's configuration mode supports the EPC serial protocol and that the JTAG chain ordering matches the Quartus programmer's expected device index. Note that newer Intel/Altera FPGAs use Active Serial (AS) configuration with EPCQ devices instead of EPC devices; EPC20LC20U is intended for legacy FPGA families only.
This page synthesizes distributor availability, drop-in alternatives from the same Altera/Intel EPC configuration family, and practical design notes for legacy FPGA configuration that are not found in any single manufacturer datasheet.
Drop-in alternatives for EPC20LC20U β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC20LC20U (same form factor and footprint) β differing in Memory Type, Package, Mounting Type, Configuration Interface, Memory Size.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPC2LC20
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPC2LC20N
β Drop-Inβ In Stock
$7.4 / Unit
View Datasheet βEPC2LI20
β Drop-Inβ In Stock
$5.95 / Unit
View Datasheet βEPC1LC20
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEPC4QC100
β Drop-Inβ In Stock
$11.4 / Unit
View Datasheet βEPC16UC88
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPC1441LC20
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPC20LC20U Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera Corporation (now Intel) |
| Function | FPGA Configuration Device (Serial Configuration PROM) |
| Memory Type | Non-volatile configuration memory |
| Configuration Interface | Serial (DATA, DCLK, nCS, nINIT_CONF, nSTATUS, OE) |
| Operating Voltage | 5.0 V (typical) |
| Absolute Maximum DC Input | -0.3 V to 7.0 V |
| Transient Input Tolerance | -2.0 V undershoot to 7.0 V overshoot (<100 mA, <20 ns) |
| Package Type | PLCC-20 (J-lead, plastic leaded chip carrier) |
| Pin Count | 20 |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Compatible FPGA Families | Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX, ACEX, early Cyclone |
| In-System Programming | Supported via JTAG / Quartus programmer |
| Lifecycle Status | Obsolete / Last-time-buy in distribution |
EPC20LC20U Pin Configuration
| Pin 1 | nSTATUS β Open-drain status output to FPGA; pulled low during configuration error |
| Pin 2 | DCLK β Configuration clock input from FPGA |
| Pin 3 | DATA β Serial configuration data output to FPGA |
| Pin 4 | nCS β Chip-select input (active low) |
| Pin 5 | OE β Output enable (active high) |
| Pin 6 | nINIT_CONF β Initiate configuration input (active low) |
| Pin 7 | VCC β +5.0 V supply |
| Pin 8 | GND β Ground |
| Pin 9 | TDI β JTAG test data input |
| Pin 10 | TDO β JTAG test data output |
| Pin 11 | TMS β JTAG test mode select |
| Pin 12 | TCK β JTAG test clock |
| Pin 13 | NC β Not connected (per datasheet) |
| Pin 14 | NC β Not connected (per datasheet) |
| Pin 15 | VCC β +5.0 V supply |
| Pin 16 | GND β Ground |
| Pin 17 | NC β Not connected (per datasheet) |
| Pin 18 | NC β Not connected (per datasheet) |
| Pin 19 | NC β Not connected (per datasheet) |
| Pin 20 | NC β Not connected (per datasheet) |
Typical Applications
EPC20LC20U is suitable for 6 applications: Legacy Altera FLEX 6000 FPGA Configuration, Altera FLEX 10K / APEX 20K Boot Memory, Industrial PLC and Process Control Boards, Telecommunications Line Card Configuration, Military and Aerospace Retrofits, Engineering Development and Prototyping Boards.
Legacy Altera FLEX 6000 FPGA Configuration
EPC20LC20U stores the configuration bitstream for Altera FLEX 6000 series FPGAs (EPF6010, EPF6016, EPF6024A) at power-up, streaming the data serially through the DATA/DCLK chain per the Altera serial configuration protocol. With 5.0 V operation and PLCC-20 socket compatibility, it is a robust solution for industrial legacy systems that still ship FLEX 6000 designs. The PLCC socket enables quick bitstream swaps during engineering development and field firmware updates. Unlike newer EPCQ AS-mode parts, the EPC20LC20U supports the legacy PS-mode protocol used by FLEX 6000, making it irreplaceable for those designs without a PCB respin.
Recommended
Altera FLEX 10K / APEX 20K Boot Memory
Large Altera FPGAs such as FLEX 10K (EPF10K50, EPF10K100) and APEX 20K (EP20K200, EP20K400) require multi-megabit configuration bitstreams that the EPC20LC20U reliably stores and streams at power-up. The 5.0 V supply rail and PLCC-20 footprint match the original Altera reference designs, eliminating the need for level shifters or PCB redesign. Designers benefit from in-system JTAG programming via Quartus, which allows field firmware updates without removing the configuration PROM from the board.
Recommended
Industrial PLC and Process Control Boards
Legacy industrial PLCs and process-control boards based on Altera FLEX 10K or APEX 20K FPGAs use EPC20LC20U as the primary boot memory because the PLCC-20 package supports socketed field service and the 5.0 V supply matches industrial 24V-bus-derived rails. The wide operating temperature range tolerates factory-floor thermal stress, and the in-system JTAG programming allows technicians to update firmware without removing the board from the chassis. This is critical for long-lifecycle industrial systems (15-20 year service life) that must remain supportable long after the original FPGA family has been discontinued.
Recommended
Telecommunications Line Card Configuration
Telecommunications line cards built around Altera FLEX 10K and APEX families deploy EPC20LC20U as the configuration memory because its 5.0 V supply rail, PLCC-20 mechanical form factor, and deterministic serial-configuration protocol meet telecom reliability requirements. Engineers value the JTAG-style in-system programming for remote firmware updates across the central-office equipment base. The PLCC-20 package also enables easy field replacement without specialized tooling.
Recommended
Military and Aerospace Retrofits
Defense and aerospace retrofits of legacy Altera-based systems (avionics, radar signal processing, secure communications) use EPC20LC20U as the configuration memory because the part has decades of documented reliability in MIL-spec environments. The PLCC-20 package withstands vibration and thermal cycling, and the 5.0 V supply matches legacy avionics power buses. Long-term spare-parts availability from authorized distributors is critical for program sustainability.
Recommended
Engineering Development and Prototyping Boards
University labs and engineering development boards use socketed EPC20LC20U configurations so students and engineers can swap configuration bitstreams quickly during RTL bring-up and timing-closure iterations. The PLCC-20 socket enables rapid PROM reprogramming without soldering, dramatically accelerating debug cycles. Quartus Programmer handles bitstream loading via JTAG, supporting both .pof (PROM Object File) and .sof (SRAM Object File) workflows for legacy FLEX and ACEX devices.
Recommended
Recommended Products Summary
Engineering reference data for EPC20LC20U β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC2LC20 | EPC2LC20N | EPC2LI20 | EPC1LC20 | EPC4QC100 |
|---|---|---|---|---|---|---|
| Package | PLCC-20 (J-lead) | PLCC-20 (J-lead) - same | PLCC-20 (J-lead) - same | PLCC-20 (J-lead) - same | PLCC-20 (J-lead) - same | PLCC-20 (J-lead) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Function | FPGA Configuration Memory | FPGA Configuration Memory | FPGA Configuration Memory | FPGA Configuration Memory (industrial temp) | FPGA Configuration Memory (smaller) | FPGA Configuration Memory (larger) |
| Operating Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Interface | Serial (DATA/DCLK) | Serial (DATA/DCLK) | Serial (DATA/DCLK) | Serial (DATA/DCLK) | Serial (DATA/DCLK) | Serial (DATA/DCLK) |
| Bitstream Capacity | EPC2 family (mid) | Same as EPC2 | Same as EPC2 | Same as EPC2 | ~50% smaller (EPC1) | ~2x larger (EPC4) |
| Lifecycle Status | Obsolete / Last-time-buy | Obsolete / Last-time-buy | Obsolete / Last-time-buy | Obsolete / Last-time-buy | Obsolete / Last-time-buy | Obsolete / Last-time-buy |
Key Differentiators
- PLCC-20 socket compatibility for legacy designs (vs EPC2LI20)
- Higher bitstream capacity vs EPC1 family (vs EPC1LC20)
- Drop-in compatibility with EPC2LC20 base part (vs EPC2LC20)
Design Notes
Do not attempt to use the EPC1LC20 as a drop-in for EPC20LC20U just because both share the PLCC-20 footprint. EPC1 has roughly half the bitstream capacity of EPC2, so designs targeting FLEX 10K or APEX 20K FPGAs will fail to configure if the .pof exceeds the EPC1 limit. Always verify the target FPGA's .pof size against the EPC variant's capacity table in the Altera Configuration Devices datasheet before substituting.
EPC20LC20U requires a clean 5.0 V supply with adequate decoupling. Place a 0.1 uF ceramic capacitor close to each VCC pin and a bulk 10 uF tantalum or aluminum electrolytic on the supply rail. The absolute maximum transient tolerance is -2.0 V undershoot / +7.0 V overshoot for input currents under 100 mA and periods shorter than 20 ns; longer or larger transients can permanently damage the device. Add TVS diodes on the supply rail for industrial environments.
Keep the DATA and DCLK traces short and matched to minimize skew during configuration. Route them away from switching power converters and high-frequency clocks to avoid coupling noise that can corrupt the configuration bitstream. The PLCC-20 socket should be ground-referenced with multiple GND pins stitched to a low-impedance ground plane. If the configuration chain spans multiple FPGAs, add proper series-termination resistors on DCLK at each load to prevent reflections.
During configuration, the FPGA drives DCLK back to the EPC at frequencies up to tens of MHz; ensure the trace impedance is controlled (typically 50 ohm single-ended) and that the FPGA's DCLK input is properly terminated. Long stubs or improper grounding can cause intermittent configuration failures that are difficult to diagnose. Use an oscilloscope to verify clean DCLK edges and stable DATA setup/hold times at the FPGA side during initial bring-up.
The PLCC-20 package has moderate thermal resistance typical of plastic J-lead packages. In enclosed industrial enclosures with ambient temperatures above 60C, verify the EPC20LC20U junction temperature stays below 125C by estimating power dissipation (typically under 100 mW at 5.0 V) and applying standard junction-rise calculations. Forced-air cooling is rarely required but recommended for high-altitude or sealed enclosures.
Compliance Information
RoHS / REACH / lead-free compliance not stated in available web data. The EPC family predates RoHS; original parts likely non-RoHS, with RoHS-compliant variants available under different date codes. EPC20LC20U is not AEC-Q100 qualified (it is a configuration memory IC, not an automotive analog/digital IC).
