EPM9560RC-304 - MAX 9000 CPLD, 12K Gates, 560 Macrocells | Altera
MPN: EPM9560RC-304 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85 | $850.00 |
| 100 | $76 | $7,600.00 |
| 500 | $68 | $34,000.00 |
| 1,000 | $62 | $62,000.00 |
EPM9560RC-304 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, CPLDs belong to programmable logic devices (PLDs), which sit alongside FPGAs as the two main classes of user-programmable digital semiconductors. CPLDs are typically chosen over FPGAs for glue-logic, bus-interface, state-machine, and power-up deterministic applications because of their deterministic timing, non-volatile configuration, and instant-on behavior.
Key features of the EPM9560RC-304 include 216 user I/O pins, a maximum operating frequency of 117.6 MHz (for the -15 speed grade), a propagation delay of approximately 15 ns at the -15 grade (13.4 ns for the -12 grade), and dual 3.3 V / 5 V I/O support through MultiVolt I/O pins. The device is housed in a 304-pin Power Quad Flat Pack (RQFP/PQFP-G304) with a JEDEC JESD-30 code of S-PQFP-G304, and operates over the commercial temperature range.
The MAX architecture partitions logic into Logic Array Blocks (LABs), each containing 16 macrocells, and connects them through the programmable interconnect array (PIA). This design delivers predictable, pin-to-pin propagation delays that are independent of routing complexity, a key advantage over SRAM-based FPGAs in timing-critical control applications. The 5.0-V ISP and JTAG chain compliance simplify board-level bring-up and field updates.
Typical applications include high-density glue logic, bus bridging and interface translation, peripheral controllers in telecom and networking equipment, industrial control systems, and legacy 5 V logic replacement. The wide I/O count also suits pin-intensive designs such as parallel bus arbitration, FIFO control, and address decoding.
When designing with the EPM9560RC-304, ensure the PCB footprint matches the 304-pin RQFP land pattern (typically 1.0 mm or 0.8 mm pitch, see the package mechanical drawing) and provide a JTAG header for in-system programming. Decoupling must follow Altera's recommended 0.1 uF / 0.01 uF placement near each VCC pin group.
This page synthesizes distributor pricing, drop-in same-package alternatives from the Altera MAX 9000 family, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EPM9560RC-304 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RC-304 (same form factor and footprint) β differing in Package, Logic Array Blocks (LABs), In-System Programmability, Architecture, Configuration Memory.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC304-15
β Drop-Inβ In Stock
$9.4 / Unit
View Datasheet βEPM9560RC304-12
β Drop-Inπ Reference alternative (not in catalog)
EPM9560RC304-15N
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9560RC304-2N
β Drop-Inβ In Stock
$149 / Unit
View Datasheet βEPM9560ARC304-10F
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9560RC-304 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| Flip-Flops | 772 |
| User I/O Pins | 216 |
| Package | 304-pin RQFP / PQFP-G304 |
| JEDEC Package Code | S-PQFP-G304 |
| Process Technology | CMOS EEPROM |
| Supply Voltage (VCCINT) | 5.0 V |
| MultiVolt I/O Support | 3.3 V / 5 V |
| Maximum Frequency (-15 grade) | 117.6 MHz |
| Propagation Delay (-12 grade) | 13.4 ns |
| Propagation Delay (-15 grade) | 15 ns |
| In-System Programming | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature (Commercial) | 0C to +70C |
| Mounting Type | Surface Mount |
EPM9560RC-304 s-pqfp-g304 Pin Configuration Guide
Pin configuration for EPM9560RC-304 (s-pqfp-g304 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC-304.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RC-304 is suitable for 6 applications: High-Density Glue Logic Replacement, Bus Interface Bridging and Protocol Translation, Industrial Control and Automation Logic, Telecom Peripheral and Backplane Controllers, Legacy 5 V Logic Board Replacement, Test and Measurement Front-End Logic.
High-Density Glue Logic Replacement
The EPM9560RC-304 is ideally suited for replacing multiple discrete 74LS/74HC TTL/CMOS glue-logic chips with a single programmable device. With 560 macrocells and 216 user I/O, it absorbs entire boards of address decoders, chip-select generators, and bus-control logic. Unlike FPGAs, its EEPROM-based non-volatile MAX architecture delivers instant-on behavior with no external boot PROM, and pin-to-pin propagation delays remain deterministic regardless of internal routing density.
Recommended
Bus Interface Bridging and Protocol Translation
The EPM9560RC-304's 216 MultiVolt I/O pins support both 3.3 V and 5 V buses on the same device, making it ideal for bridging legacy 5 V peripherals to modern 3.3 V processors. The 117.6 MHz fMAX (at -15 grade) comfortably handles standard parallel bus protocols including PCI, ISA, and VME arbitration, while 560 macrocells provide ample state-machine capacity for protocol conversion. JTAG ISP allows field firmware updates without removing the device from the board.
Recommended
Industrial Control and Automation Logic
In industrial control systems the EPM9560RC-304 consolidates PLC-style sequencing, motor-control state machines, and safety interlocks into a single non-volatile device. Its 5 V tolerant MultiVolt I/O directly drives 24 V optocoupler and relay interfaces through external drivers, while 772 flip-flops support complex timing diagrams and shift-register chains. EEPROM-based configuration provides fail-safe startup with no boot delay, critical for deterministic industrial response times.
Recommended
Telecom Peripheral and Backplane Controllers
Telecom systems rely on the EPM9560RC-304 for backplane arbitration, clock distribution, and HDB3/AMI line-encoding tasks where deterministic timing is mandatory. With 216 I/O it directly interfaces multi-drop TDM buses and serial backplane links without external transceivers. The MAX architecture's predictable timing simplifies timing-budget closure in T1/E1 and SONET-adjacent designs, and the JTAG interface supports board-level boundary-scan for high-pin-count backplane bring-up.
Recommended
Legacy 5 V Logic Board Replacement
The EPM9560RC-304 is the canonical drop-in replacement for end-of-life 5 V programmable logic arrays (PAL/GAL) and older bipolar PLDs. Its 5 V VCCINT and MultiVolt I/O match original supply rails, so existing 5 V boards can be modernized without redesigning the power tree. 560 macrocells typically replace dozens of discrete 22V10/20V8 devices, freeing board space and reducing component count while preserving proven system firmware.
Recommended
Test and Measurement Front-End Logic
In test and measurement instruments the EPM9560RC-304 implements front-end sequencing, range switching, multiplexer control, and ADC/DAC handshake logic with deterministic timing. The 117.6 MHz fMAX and 772 flip-flops support high-speed counter and trigger subsystems, while 216 user I/O drive complex front-panel switch matrices. EEPROM configuration also makes the device attractive in safety-critical test rigs because configuration is retained through power loss without boot latency.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC-304 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-15 | EPM9560RC304-12 | EPM9560RC304-15N | EPM9560RC304-2N | EPM9560ARC304-10F |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 304-pin RQFP / PQFP-G304 | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/O Pins | 216 | 216 | 216 | 216 | 216 | 216 |
| Supply Voltage | 5.0 V (MultiVolt 3.3/5 V I/O) | 5.0 V | 5.0 V | 5.0 V (Pb-free) | 5.0 V | 5.0 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest-density member of MAX 9000 family (vs EPM9480RC240-20)
- Instant-on non-volatile configuration (vs SRAM-based FPGAs (e.g., Cyclone IV))
- MultiVolt I/O for mixed-voltage systems (vs Single-voltage 5 V CPLDs)
Design Notes
Estimated: The 304-pin RQFP (PQFP-G304) package uses a 0.5 mm or 0.8 mm pitch (verify against the package mechanical drawing in the MAX 9000 datasheet before layout). Provide at least four-layer PCB construction with continuous ground planes under the device for signal-integrity and thermal performance. Add 0.1 uF decoupling capacitors every 5-10 VCC pins and a single bulk 10-47 uF tantalum or ceramic near the device. JTAG header (TCK/TMS/TDI/TDO/TRST) must be accessible for in-system programming.
Do not confuse the EPM9560RC-304 with the EPM9480 or EPM9400 - these are different-density members of the MAX 9000 family with fewer macrocells and different pin counts. When migrating an existing EPM9560RC-304 board, confirm the -12 vs -15 speed grade in the original schematic because the -12 grade (13.4 ns / 125 MHz) is faster than -15 (15 ns / 117.6 MHz) and may affect timing closure if downgraded. Also verify the 'N' suffix indicates Pb-free terminal finish for RoHS compliance.
Estimated: With 216 user I/O switching simultaneously at 117.6 MHz, simultaneous-switching output (SSO) noise can couple into VCCIO rails and degrade MultiVolt I/O thresholds. Use guard traces or ground-signal-ground pin assignments where possible, and isolate 3.3 V and 5 V I/O banks with separate decoupling. For designs exceeding 100 MHz I/O rates, simulate signal-integrity with the IBIS model from Altera's design resources before committing to layout.
Compliance Information
RoHS / lead-free status not explicitly stated in the verified web data; the EPM9560RC304-15N variant carries Pb-free terminal finish (N suffix) per DigiKey listing. AEC-Q100 qualification not applicable for legacy programmable logic. Original Altera product page does not publish a complete REACH or conflict-minerals statement for this part.
