EPM9560RC304-15N - MAX 9000 CPLD 560 Macrocells | Altera/Intel
MPN: EPM9560RC304-15N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 250 | $22.95 | $5,737.50 |
| 500 | $19.8 | $9,900.00 |
EPM9560RC304-15N Overview
What is a CPLD? A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/PLDs (small PAL/GAL-style glue logic) and FPGAs in the programmable logic taxonomy. Compared with FPGAs, CPLDs are typically flash- or EEPROM-backed, deterministic, have predictable pin-to-pin propagation delays in the nanosecond range, and boot instantly at power-up - making them ideal for bus decoding, address mapping, power-sequencing logic, and high-speed control rather than large parallel DSP or register-heavy data-pipeline designs.
Key features of the EPM9560RC304-15N include 560 macrocells across 16 logic array blocks (LABs), 12,000 usable gates, 304 user I/O pins via the RQFP-304 package, and -15 speed grade indicating a 15 ns pin-to-pin propagation delay. The MAX 9000 family also provides programmable interconnect, 5 V tolerant inputs and outputs, and the JTAG-based ISP for boundary-scan and field reprogramming. The -15N suffix indicates the commercial operating temperature grade and lead-free / RoHS-compliant package marking.
Typical applications include high-speed address decoding for memory and peripheral buses, 32-bit and 64-bit microprocessor glue logic, bus-interface bridging (PCI, ISA, VME, EISA), industrial control state machines, and ASIC-prototype replacement. The 304-pin RQFP package and 117.6 MHz fMAX make this CPLD well suited to designs requiring many parallel I/O channels in a single non-volatile device.
When designing with this part, observe 5 V supply rail decoupling (>=0.1 uF ceramic per VCC pin), keep JTAG TCK below 10 MHz for reliable ISP, and ensure unused I/O pins are configured as outputs or terminated per Altera application note guidelines to avoid floating-input noise. The 304-pin RQFP footprint is shared with the broader MAX 9000 family, simplifying PCB reuse across EPM9400/EPM9480/EPM9560 density points and speed grades.
This page consolidates verified distributor pricing, JTAG-programmable drop-in alternatives within the MAX 9000 family, and practical design notes not duplicated from the original datasheet. Engineers familiar with legacy Altera design flows (MAX+PLUS II or Quartus MAX device support) will find the EPM9560RC304-15N fully supported by legacy toolchains, though new designs targeting Intel MAX II/MAX V CPLDs benefit from lower static power and modern packaging.
Drop-in alternatives for EPM9560RC304-15N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RC304-15N (same form factor and footprint) β differing in Package, Speed Grade, Logic Array Blocks (LABs), User I/O Pins, Architecture.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC304-15
β Drop-Inβ In Stock
$9.4 / Unit
View Datasheet βEPM9560RC304-15C
β Drop-Inβ In Stock
$24.5 / Unit
View Datasheet βEPM9560RC304-15F
β Drop-Inβ In Stock
$18.75 / Unit
View Datasheet βEPM9560RC304-10
β Drop-Inβ In Stock
$17.6 / Unit
View Datasheet βEPM9560ARC304-10F
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9480RC304-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9560RC304-15N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 (estimated from 560 macrocells) |
| Maximum Operating Frequency (fMAX) | 117.6 MHz |
| Pin-to-Pin Propagation Delay | 15 ns (-15 speed grade) |
| Supply Voltage (VCCINT) | 5 V |
| Package | RQFP-304 |
| User I/O Count | 304 (package-level) |
| Process Technology | High-performance CMOS EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature Grade | Commercial (suffix N) |
| RoHS Status | Compliant (lead-free per suffix N marking) |
EPM9560RC304-15N rqfp-304 Pin Configuration Guide
Pin configuration for EPM9560RC304-15N (rqfp-304 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC304-15N.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RC304-15N is suitable for 6 applications: High-Speed Bus Address Decoding, 32/64-bit Microprocessor Glue Logic, Industrial Control State Machines, ASIC Prototype and Logic Integration, Legacy PCI/ISA/VME Bus Bridge Logic, Test and Measurement Equipment.
High-Speed Bus Address Decoding
The EPM9560RC304-15N's 117.6 MHz fMAX and 15 ns pin-to-pin delay make it well suited to address-decoding and chip-select generation for high-speed memory and peripheral buses. With 560 macrocells and 304 user I/Os, it can simultaneously decode multiple address regions and generate individual chip-enable signals for large memory banks. The non-volatile EEPROM configuration boots at power-up with deterministic timing, eliminating the FPGA-style configuration-delay window. Placed on the address/control bus between a microprocessor and peripherals, it replaces 5-15 discrete PAL/GAL devices, reducing board area. The 5 V tolerant I/Os are ideal for legacy 5 V ISA, VME, and EISA bus architectures.
Recommended
32/64-bit Microprocessor Glue Logic
The EPM9560RC304-15N serves as a centralized glue-logic hub in 32-bit and 64-bit microprocessor systems, integrating wait-state generators, bus arbiters, interrupt controllers, and timing-state machines into one non-volatile device. The 560 macrocells and 304 I/Os provide sufficient headroom for modern CPU companion functions while maintaining deterministic 15 ns propagation delays. Unlike FPGAs, the EEPROM-backed MAX 9000 boots instantly at power-on, eliminating the need for external configuration memory in safety-critical or deterministic-startup applications. Combined with JTAG-based in-system programmability, field updates are possible without removing the device from the board.
Recommended
Industrial Control State Machines
The EPM9560RC304-15N's deterministic timing and 304 I/Os suit industrial-control state machines requiring many parallel sensor and actuator lines. Its 15 ns propagation delay enables microsecond-scale control-loop latency, while 12,000 usable gates support multi-axis state machines, encoder-decoders, and protocol bridges. The MAX 9000 family supports 5 V tolerant I/O, simplifying integration with legacy industrial sensors. The JTAG-based in-system programmability (IEEE 1149.1) enables boundary-scan production testing and field firmware updates. Industrial-grade variants like EPM9560RC304-15F extend the operating-temperature range to -40C to +85C for harsh environments.
Recommended
ASIC Prototype and Logic Integration
The EPM9560RC304-15N is widely used as an ASIC prototype device, allowing engineers to validate complex glue-logic designs before committing to masked-ASIC fabrication. With 12,000 gates and 560 macrocells, it can absorb most peripheral-interface and bus-control functions that would otherwise justify an ASIC spin. Designers using MAX+PLUS II or Quartus can convert prototype designs to ASIC netlists once the logic stabilizes, dramatically reducing time-to-market risk. The 304-pin RQFP package and JTAG interface are well documented for ASIC-emulation evaluation boards. For low-volume production runs (100s to 1000s of units), the CPLD often replaces the ASIC entirely.
Recommended
Legacy PCI/ISA/VME Bus Bridge Logic
The EPM9560RC304-15N's 304 user I/Os and 5 V tolerant interface make it ideal for legacy PCI, ISA, and VME bus bridges, where it implements address-latch, data-buffer-control, and arbitration logic. Its 117.6 MHz fMAX supports PCI 33 MHz bus timing with timing margin, and 15 ns propagation delays accommodate ISA-style non-pipelined protocols. The non-volatile configuration eliminates bus-glitch during power-up that is typical of SRAM-based FPGAs, a critical concern for hot-swap-capable VME systems. Combined with the JTAG boundary-scan interface, the device simplifies PCBA-level interconnect test for backplane assemblies.
Recommended
Test and Measurement Equipment
The EPM9560RC304-15N provides reconfigurable logic for test-and-measurement instruments such as logic analyzers, protocol analyzers, and bench-top ATE. Its 304 I/Os handle high-channel-count stimulus/response patterns, while the 560 macrocells implement timing generators, pattern sequencers, and protocol-state machines. The JTAG-based ISP (IEEE 1149.1) boundary-scan chain doubles as a production-test interface, simplifying fixture design. The deterministic 15 ns propagation delay is well suited to digital-pattern timing budgets. The MAX 9000 family's mature MAX+PLUS II toolchain enables rapid waveform-pattern iteration during instrument development.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC304-15N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-15 | EPM9560RC304-15C | EPM9560RC304-15F | EPM9560RC304-10 | EPM9560ARC304-10 | EPM9480RC304-15 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-304 | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same | RQFP-304 - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 480 |
| Speed Grade (tPD) | 15 ns | 15 ns | 15 ns | 15 ns | 10 ns | 10 ns | 15 ns |
| Operating Temperature Grade | Commercial (N suffix) | Commercial | Commercial | Industrial (-40C to +85C) | Commercial | Commercial | Commercial |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG | IEEE 1149.1 JTAG |
Key Differentiators
- Lead-free/RoHS-compliant commercial temperature grade (vs EPM9560RC304-15)
- Industrial temperature range option available in same package (vs EPM9560RC304-15F)
- Higher speed-grade option in same package (vs EPM9560RC304-10)
- Lower-density drop-in option for cost-sensitive designs (vs EPM9480RC304-15)
Design Notes
Estimated: The EPM9560RC304-15N draws approximately 200-400 mA quiescent ICC at 5 V with all I/Os static, depending on configuration and switching activity. Decouple each VCC/VSS pin pair with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF tantalum or ceramic bulk capacitor near the package. The 304-pin RQFP package has multiple VCC/VSS pin pairs distributed around the perimeter - verify all pairs are decoupled. Avoid switching the entire device simultaneously to limit di/dt-induced supply droop.
The 304-pin RQFP package has 0.5 mm lead pitch and gull-wing leads. Use a 4-layer PCB with continuous ground plane beneath the device for thermal dissipation and controlled impedance on critical JTAG traces. Route JTAG TCK, TMS, TDI, TDO as a bus with maximum 10 MHz TCK for reliable ISP. Keep TCK trace length under 100 mm and add a 22-ohm series termination near the source to suppress ringing. Provide a pull-up on TCK and TMS, and a pull-up or pull-down on TDI per Altera JTAG guidelines.
Common pitfalls include: (1) floating JTAG TCK causing unintended ISP mode entry - always tie TCK to a defined logic level via pull-up when not programming; (2) configuring unused I/O pins as inputs without pull-ups, leading to increased ICC and possible oscillation - configure unused pins as outputs driving a defined logic level or use Altera's default weak pull-up setting; (3) exceeding 5.0 V VCC tolerance on I/Os - the MAX 9000 family is 5 V-only and not 3.3 V tolerant on inputs. For new designs, prefer MAX II or MAX V CPLDs.
For high-speed bus-interface designs using the EPM9560RC304-15N, group I/O pins by bus function (address, data, control) to minimize internal macrocell routing delays. Place clock-input pins adjacent to the LAB that drives the global clock network - on RQFP-304 this is typically the upper-left quadrant. Use Altera MAX+PLUS II or Quartus floorplanning tools to lock critical-pin assignments. Maintain 50-ohm controlled impedance on clock and JTAG traces; other signals may use 33-ohm or 50-ohm depending on trace length.
Compliance Information
RoHS compliance indicated by N suffix per Altera/Intel part-number convention. Lead-free per N suffix. Halogen-free and conflict-minerals status not explicitly stated in verified web data; flagged as unknown. Not AEC-Q100 qualified - this is a commercial/industrial grade part, not automotive.
