EPM9560RC240-20 - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
MPN: EPM9560RC240-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $148 | $14,800.00 |
| 250 | $135 | $33,750.00 |
| 500 | $122 | $61,000.00 |
EPM9560RC240-20 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital logic IC that occupies the middle ground between discrete PAL/GAL devices and high-density FPGAs. Within the programmable logic taxonomy, CPLDs sit alongside FPGAs under the broader category of Programmable Logic Devices (PLDs). MAX 9000 devices are particularly valued for their deterministic timing, predictable pin-to-pin delays, and 5V tolerant I/O - characteristics that legacy industrial designs often require.
Key features include 4.75V to 5.25V single-supply operation, a 100 MHz maximum internal frequency, in-system programmability via IEEE Std 1149.1 (JTAG) and Altera's proprietary programming interfaces, and a commercial operating temperature range of 0C to 70C. The 240-pin RQFP package provides a thermal resistance of approximately 22 C/W (junction-to-ambient, typical) and a 31.0 mm x 31.0 mm body suitable for socketed or surface-mount legacy boards. JTAG boundary-scan support simplifies board-level testability.
Architecturally, the MAX 9000 family uses a uniform interconnect architecture called the Programmable Interconnect Array (PIA), which routes signals between the 35 Logic Array Blocks (LABs) and the I/O elements. Each LAB contains 16 macrocells; the 560-macrocell density allows designers to integrate wide address decoders, register-rich state machines, and asynchronous glue logic in a single chip, replacing multiple 22V10/16V8-style PALs and 74LS discrete glue.
Typical applications include legacy industrial control boards, telecommunications backplane glue logic, PCI/ISA bus interface bridges, and bus-width translation/muxing on legacy microcomputer systems. The 5V-tolerant I/Os also suit retrofit designs where modern 3.3V-only FPGAs would require level shifters.
When designing with the EPM9560RC240-20, verify that the JTAG chain order and I/O assignments match the legacy schematic; the 240-RQFP footprint is shared across many MAX 9000 variants, so pin-compatible migration within the family is straightforward. Plan for in-system programming header access to support field updates.
This page synthesizes distributor pricing, pin-compatible MAX 9000 alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EPM9560RC240-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPM9560RC240-20 (same form factor and footprint) β differing in Package, Operating Temperature, Programming Interface, Logic Array Blocks (LABs), Process Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC240-15
β Drop-Inβ In Stock
$174.72 / Unit
View Datasheet βEPM9560RC240-10
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Contact for price
View Datasheet βEPM9560RC240-12
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$9.95 / Unit
View Datasheet βEPM9560ARC240-10
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$28.8 / Unit
View Datasheet βEPM9560ARC240-10N
β Drop-Inβ In Stock
$19.5 / Unit
View Datasheet βEPM9560RC240-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Series | MAX 9000 PLD Family |
| Programmable Type | In System Programmable |
| Number of Macrocells | 560 |
| Number of Gates | 12,000 |
| Number of Logic Elements/Blocks | 35 LABs |
| Number of User I/Os | 191 |
| Propagation Delay (tPD max) | 20 ns |
| Maximum Internal Frequency | 100 MHz |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V |
| Technology | CMOS, EEPROM-based |
| Operating Temperature | 0C to 70C (Commercial) |
| Mounting Type | Surface Mount |
| Package / Case | 240-BFQFP Exposed Pad (RQFP-240) |
| Supplier Device Package | 240-RQFP |
| Programming Interface | JTAG (IEEE 1149.1), Altera proprietary |
| Product Status | Obsolete |
EPM9560RC240-20 240-rqfp Pin Configuration Guide
Pin configuration for EPM9560RC240-20 (240-rqfp package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-20.
Refer to the datasheet for full pin configuration.
Typical Applications
EPM9560RC240-20 is suitable for 6 applications: Legacy Industrial Bus Interface Glue Logic, PCI/ISA Bridge and Width Translation, Telecommunications Backplane Glue Logic, Retrofit Designs Requiring 5V Tolerance, Asynchronous State Machine Consolidation, Wide Address Decoder and Memory Mapper.
Legacy Industrial Bus Interface Glue Logic
The EPM9560RC240-20 is well-suited to legacy industrial backplane designs where 5V TTL signaling and deterministic pin-to-pin delays are required. With 560 macrocells and 191 user I/Os, the part can integrate address decoding, wait-state generation, and bus arbitration across ISA, VME, or PC/104 buses in a single chip. Its 20 ns tPD provides setup/hold margin at bus frequencies up to 25 MHz, and the 5V-tolerant I/Os interface directly to 74LS/74HC logic without level shifters.
Recommended
PCI/ISA Bridge and Width Translation
The EPM9560RC240-20 excels as a PCI-to-ISA bridge or 32-bit/16-bit width translator in legacy x86 motherboards and add-in cards. The 191 user I/Os and 12,000 usable gates are sufficient to implement both the bus-master arbitration logic and the data-path steering registers in one device. Designers value the deterministic 20 ns tPD for meeting PCI 33 MHz setup/hold requirements, and the in-system programmability supports late-stage design changes without re-spinning the PCB.
Recommended
Telecommunications Backplane Glue Logic
In telecommunications equipment such as TDM backplanes, E1/T1 framers, and central-office switches, the EPM9560RC240-20 replaces multiple discrete PAL/GAL devices and 74-series glue. The 560 macrocells integrate channelized state machines, frame-alignment logic, and alarm-monitor registers, while the 5V supply matches the legacy -48V-to-+5V converter rails common in telecom bays. The 240-RQFP package is socket-friendly, simplifying field replacement on installed equipment.
Recommended
Retrofit Designs Requiring 5V Tolerance
When modernizing legacy boards that use 5V TTL logic, designers often cannot drop in a 3.3V-only FPGA. The EPM9560RC240-20's 5V VCCINT and 5V-tolerant I/Os make it the natural choice for retrofits that need additional logic capacity without redesigning the power tree. The non-volatile EEPROM configuration means instant-on operation, eliminating the boot-PROM overhead required by SRAM-based FPGAs. The 191 user I/Os also reduce the need for additional buffer/expansion chips.
Recommended
Asynchronous State Machine Consolidation
Designers use the EPM9560RC240-20 to consolidate multiple asynchronous state machines (watchdog timers, sequencers, motor controllers, and protocol converters) into a single chip. With 560 macrocells available, the part typically holds 25-35 state machines depending on width and depth. The deterministic tPD timing avoids the metastability pitfalls that plague SRAM-FPGA-based state machines, and the EEPROM-backed configuration retains state through power cycles - critical for industrial safety interlocks.
Recommended
Wide Address Decoder and Memory Mapper
The EPM9560RC240-20 is ideal for building wide address decoders and memory-mapping circuits in 32-bit embedded systems. The 191 user I/Os accommodate up to 24 address lines plus 16 chip-select outputs without external expansion, and the 20 ns tPD supports memory access times down to about 70 ns. Designers replace discrete 74LS138/74LS139 decoder trees with a single programmable device, simplifying board layout and improving noise immunity through reduced chip count.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-15 | EPM9560RC240-10 | EPM9560RC240-12 | EPM9560ARC240-10 | EPM9560ARC240-10N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 240-RQFP (BFQFP exposed pad) | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same | 240-RQFP - same |
| Propagation Delay (tPD max) | 20 ns | 15 ns (-25%) | 10 ns (-50%) | 12 ns (-40%) | 10 ns (-50%) | 10 ns (-50%) |
| Macrocells | 560 | 560 (same) | 560 (same) | 560 (same) | 560 (same) | 560 (same) |
| User I/Os | 191 | 191 (same) | 191 (same) | 191 (same) | 191 (same) | 191 (same) |
| Logic Array Blocks | 35 | 35 (same) | 35 (same) | 35 (same) | 35 (same) | 35 (same) |
| Supply Voltage | 4.75V to 5.25V | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) | 4.75V to 5.25V (same) |
| Operating Temperature | 0C to 70C (Commercial) | 0C to 70C (same) | 0C to 70C (same) | 0C to 70C (same) | -40C to 85C (Industrial) | -40C to 85C (Industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Lead-Free (N suffix) | No | No | No | No | No | Yes (lead-free) |
Key Differentiators
- Highest macrocell density in the 240-RQFP MAX 9000 family (vs EPM9480RC240-20)
- Slower speed grade but pin-compatible with faster variants (vs EPM9560RC240-15)
- Commercial temperature grade (0C to 70C) - widest availability (vs EPM9560ARC240-10)
Design Notes
The EPM9560RC240-20 requires a stable 5.0V supply (4.75V to 5.25V) with a typical ICC of approximately 200-400 mA depending on switching activity. Decouple VCCINT and VCCIO planes with 0.1uF ceramic capacitors placed within 5 mm of each supply pin, plus bulk 10-47uF tantalum or aluminum polymer caps at the board entry point. During in-system programming, peak current can surge as the EEPROM cells charge - ensure the regulator has at least 20% headroom above the steady-state ICC.
Route all 191 user I/O signals with matched trace lengths when used as a parallel bus to avoid skew. Place the JTAG header (TCK, TMS, TDI, TDO plus optional TRST) on a board edge or dedicated test point cluster to support in-field programming. The 240-RQFP package has a center thermal pad that must be soldered to a copper pour for mechanical reliability and thermal dissipation - do not leave it floating.
Estimated: in-system programming via JTAG requires the device to be in a valid user state with no conflicting drivers on TDI/TDO lines - isolate any bus drivers from the JTAG chain during programming. Do not exceed the 5.25V absolute-maximum VCCINT even briefly; over-voltage damages the EEPROM cells. When migrating from -20 to -15 or -10 speed grades, the design must be re-fitted (different timing model in MAX+PLUS II) but the pinout and bitstream structure remain identical.
Compliance Information
The MAX 9000 family was originally released before RoHS took full effect; many production lots carry tin-lead (SnPb) finish. Request a lot-specific RoHS/lead-free certificate from the distributor. AEC-Q100 is not applicable because this is a commercial-grade programmable logic device.
