IQE013N04LM6SCATMA1 - 40V 1.35mΩ OptiMOS Source-Down MOSFET | Infineon
MPN: IQE013N04LM6SCATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.85 | $1.85 |
| 10 | $1.62 | $16.20 |
| 100 | $1.38 | $138.00 |
| 500 | $1.18 | $590.00 |
| 1,000 | $1.02 | $1,020.00 |
IQE013N04LM6SCATMA1 Overview
An N-channel power MOSFET is a voltage-controlled majority-carrier device whose conduction loss is governed by R<sub>DS(on)</sub> and whose switching loss is set by the gate charge Q<sub>G</sub> and the drain-source capacitance. The OptiMOS Source-Down family places the source connection on the bottom of the die and on the PCB footprint, enabling double-sided cooling through the exposed pad and direct top-side PCB copper for the drain, which lowers thermal resistance and shrinks the required PCB area for a given R<sub>DS(on)</sub>. As a 40 V part the IQE013N04LM6 belongs to the low-voltage power MOSFET hierarchy: MOSFET → power MOSFET → N-channel enhancement mode → OptiMOS low-voltage family → Source-Down topology → semiconductor.
Key features include ±20 V maximum gate-source rating, 41 nC total gate charge at 10 V V<sub>GS</sub>, 3800 pF output capacitance C<sub>oss</sub> at 20 V V<sub>DS</sub>, and a Source-Down leadless package that simplifies thermal management. According to the manufacturer datasheet the absolute maximum ratings are defined with case temperature held at 25 °C; derating is required for higher case temperatures as shown in the safe operating diagram.
The Source-Down die architecture flips the conventional Source-on-bottom layout, allowing the drain tab to sit on the top thermal pad and the source to bond directly to the PCB. This reduces package parasitic source inductance and improves current spreading, which is critical for high di/dt switching transitions in synchronous rectification stages.
Typical applications include 12 V-24 V server and telecom point-of-load conversion, synchronous rectification in SMPS, motor drives, eMobility auxiliary loads, and USB Power Delivery high-current rails. The combination of very low R<sub>DS(on)</sub> and Source-Down thermal architecture suits space-constrained designs that previously required D²PAK footprints.
Designers should observe the ±20 V V<sub>GS</sub> limit, place the gate driver within 5 mm of the gate pad, and provide at least 50 mm² of top-side drain copper for a 100 °C/W θ<sub>JA</sub> target. The Source-Down footprint is NOT pin-compatible with traditional DFN-style PQFN footprints; verify the land pattern against the manufacturer PG-WHSON-8-1 recommendation before board rework.
This page synthesizes distributor inventory, verified drop-in and functional alternatives, and practical Source-Down layout notes that complement the manufacturer datasheet rather than restate it.
Drop-in alternatives for IQE013N04LM6SCATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IQE013N04LM6SCATMA1 (same form factor and footprint) — differing in Package, Technology, Operating Temperature Range, Drain-Source Voltage (VDS), Product Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IQE013N04LM6ATMA1
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View Datasheet →IQE008N03LM5SCATMA1
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View Datasheet →IQE036N08NM6CGATMA1
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View Datasheet →ISC011N04NM7VATMA1
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View Datasheet →IAUCN08S7L033ATMA1
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View Datasheet →IQE013N04LM6SCATMA1 Maximum Ratings & Electrical Characteristics
| FET Type | N-Channel |
| Technology | OptiMOS (trench MOSFET) |
| Drain-Source Voltage (V<sub>DS</sub>) | 40 V |
| Gate-Source Voltage (V<sub>GS</sub>) | ±20 V |
| R<sub>DS(on)</sub> max @ V<sub>GS</sub>=10 V | 1.35 mΩ |
| Continuous Drain Current (I<sub>D</sub>) at T<sub>A</sub>=25 °C | 31 A |
| Pulsed Drain Current (I<sub>DM</sub>) at T<sub>C</sub>=25 °C | 205 A |
| Power Dissipation (P<sub>D</sub>) at T<sub>A</sub>=25 °C | 2.5 W |
| Power Dissipation (P<sub>D</sub>) at T<sub>C</sub>=25 °C | 107 W |
| Total Gate Charge (Q<sub>G</sub>) @ V<sub>GS</sub>=10 V | 41 nC |
| Output Capacitance (C<sub>oss</sub>) @ V<sub>DS</sub>=20 V | 3800 pF |
| Package | PG-WHSON-8-1 (3.3 mm × 3.3 mm Source-Down PQFN) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Packaging | Tape & Reel |
| Part Family | OptiMOS Source-Down, 40 V, 3.3×3.3 PQFN |
IQE013N04LM6SCATMA1 Pin Configuration
| Pin 1 | G — Gate |
| Pin 2 | S — Source |
| Pin 3 | S — Source |
| Pin 4 | S — Source |
| Pin 5 | S — Source |
| Pin 6 | S — Source |
| Pin 7 | S — Source |
| Pin 8 | D — Drain (top thermal pad also connects to drain on Source-Down package) |
| Pin EP | Source / Thermal Pad — Source connection and primary thermal path on the bottom side; on Source-Down configuration the drain thermal pad is on the top |
Safe Operating Area (T_C = 25 °C, single pulse)
Typical Applications
IQE013N04LM6SCATMA1 is suitable for 6 applications: 12 V Synchronous Rectification in SMPS, USB Power Delivery High-Current Rails, Telecom 48 V Point-of-Load Conversion, Motor Drive H-Bridge (Low-Side Switch), Hot-Swap and OR-ing in Server PSUs, Battery Management and eMobility Auxiliary Loads.
12 V Synchronous Rectification in SMPS
The IQE013N04LM6SCATMA1 fits 12 V synchronous rectification in isolated and non-isolated SMPS topologies because its 1.35 mΩ R<sub>DS(on)</sub> at 10 V V<sub>GS</sub> minimizes conduction loss on the low-side FET, and the 40 V V<sub>DS</sub> rating provides a 3.3× safety margin above the 12 V rail including inductive ringing. The Source-Down 3.3×3.3 PG-WHSON-8-1 package reduces PCB footprint by roughly 70% compared to a D²PAK at the same R<sub>DS(on)</sub> class, enabling higher power density in telecom and server bricks. Place the part on the bottom-side source pad with top-side drain copper for double-sided cooling.
Recommended
USB Power Delivery High-Current Rails
The IQE013N04LM6SCATMA1 is suited for USB Power Delivery (USB PD) 100 W synchronous buck converters delivering 5 V/20 V at 5 A. Its 1.35 mΩ R<sub>DS(on)</sub> and 41 nC total gate charge balance conduction and switching losses at 100-300 kHz switching frequencies typical of USB PD designs. The Source-Down 3.3×3.3 mm footprint fits inside 30 mm × 30 mm travel-adapter PCBs where D²PAK parts cannot fit. According to the Infineon OptiMOS datasheet, the 40 V V<sub>DS</sub> rating provides margin above 20 V USB PD VBUS transients and cable hot-plug events.
Recommended
Telecom 48 V Point-of-Load Conversion
The IQE013N04LM6SCATMA1 functions as the low-side FET in 48 V-to-PoL buck stages where intermediate bus voltages stay below 40 V (typical 24 V or 36 V secondary rails from an isolated front-end). At these voltages the 40 V V<sub>DS</sub> rating provides adequate margin, while the 1.35 mΩ R<sub>DS(on)</sub> minimizes conduction loss at 10-25 A continuous loads typical of ASIC and FPGA core rails. The Source-Down 3.3×3.3 PG-WHSON-8-1 package reduces board area versus D²PAK alternatives by 5-7×, important in 1U and 2U telecom shelves where PCB real estate is at a premium.
Recommended
Motor Drive H-Bridge (Low-Side Switch)
The IQE013N04LM6SCATMA1 serves as the low-side switch in 12 V-24 V brushless DC motor drive H-bridges driving 10-30 A continuous loads. Its 1.35 mΩ R<sub>DS(on)</sub> at 10 V V<sub>GS</sub> keeps conduction loss under 5 W at 25 A continuous, and the Source-Down exposed thermal pad spreads heat directly into the bottom PCB copper layer for improved θ<sub>JA</sub>. Per the Infineon datasheet, the ±20 V V<sub>GS</sub> rating tolerates gate-drive transients from bootstrap high-side drivers, and the 41 nC Q<sub>G</sub> enables 25-50 kHz PWM without excessive driver losses.
Recommended
Hot-Swap and OR-ing in Server PSUs
The IQE013N04LM6SCATMA1 fits 12 V hot-swap and OR-ing FET roles in redundant server power supply designs. At 1.35 mΩ R<sub>DS(on)</sub> the IR drop across the OR-ing FET stays below 30 mV at 20 A, well within the 12 V bus tolerance. The 40 V V<sub>DS</sub> rating handles transients during hot-plug events. The Source-Down exposed pad allows the FET to share the bottom copper plane with other heat sources, lowering overall θ<sub>JA</sub>. According to the Infineon datasheet the 205 A pulsed rating supports inrush currents up to 200 µs during server mid-plane insertion.
Recommended
Battery Management and eMobility Auxiliary Loads
The IQE013N04LM6SCATMA1 is appropriate for low-voltage auxiliary loads in 24 V-36 V eMobility battery management systems, including load dump protection circuits and reverse-polarity blocking FETs. Its 40 V V<sub>DS</sub> rating handles 36 V battery transients within ISO 7637-2, while the 1.35 mΩ R<sub>DS(on)</sub> minimizes voltage drop across the blocking FET. The Source-Down 3.3×3.3 PQFN footprint simplifies integration in space-constrained BMS modules. Per Infineon datasheet, the ±20 V V<sub>GS</sub> rating tolerates 12 V/24 V jump-start events without gate-oxide stress.
Recommended
Recommended Products Summary
Engineering reference data for IQE013N04LM6SCATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IQE013N04LM6ATMA1 | IQE008N03LM5SCATMA1 | IQE036N08NM6CGATMA1 | ISC011N04NM7VATMA1 | ISC015N06NM5ATMA1 | IAUCN08S7L033ATMA1 |
|---|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-WHSON-8-1 (3.3×3.3 Source-Down) | PG-WHSON-8-1 (3.3×3.3, same family, standard Source-on-bottom) | PG-WHSON-8-1 (3.3×3.3, same Source-Down footprint) | PG-WHSON-8-1 (3.3×3.3, same family) | PG-WHSON-8-1 (3.3×3.3, same Source-Down footprint) | PG-WHSON-8-1 (3.3×3.3, same family) | PG-WHSON-8-1 (3.3×3.3, same Source-Down family) |
| V_DS max | 40 V | 40 V | 30 V | 80 V | 40 V | 60 V | 80 V |
| R_DS(on) max @ V_GS=10V | 1.35 mΩ | 1.35 mΩ | 0.8 mΩ | 3.6 mΩ | 1.1 mΩ | 1.5 mΩ | 3.3 mΩ |
| Source-Down Topology | Yes | No (standard Source-on-bottom) | Yes | No | Yes | No | Yes |
Key Differentiators
- Source-Down thermal architecture (vs IQE013N04LM6ATMA1)
- Lower R_DS(on) at 40 V in Source-Down PQFN (vs IAUCN08S7L033ATMA1)
- Compact 3.3×3.3 PQFN with 30% lower R_DS(on) than prior generation (vs D²PAK-class competitors (e.g. IRFB3207ZPBF in TO-263))
Design Notes
Estimated: at V_IN=24 V, V_OUT=12 V, I_OUT=10 A continuous synchronous rectification, the IQE013N04LM6SCATMA1 dissipates roughly (24-12) × 0.5 × 10/2 = 30 W if used as a hard-switched buck switch (calculation assumes 50% duty cycle). In practice for low-side synchronous rectification the FET sees only the conduction loss I² × R_DS(on) = 10² × 1.35 mΩ = 0.135 W, plus switching losses of ~0.5 W at 200 kHz. Always provide at least 100 mm² of bottom-side source copper and verify θ_JA against the Source-Down PG-WHSON-8-1 thermal model in the Infineon datasheet before finalizing the layout.
Source-Down configuration places the source on the bottom thermal pad and the drain on the top pad. Route the high-current drain copper on the top layer directly above the exposed pad to maximize heat spreading, and stitch the bottom source copper to the surrounding ground plane with at least 9 thermal vias (0.3 mm drill, 0.5 mm pitch). Place the gate-driver loop within 5 mm of the gate pin to minimize parasitic inductance and limit V_GS ringing under high di/dt. Source: Infineon PG-WHSON-8-1 Source-Down layout application note.
Do not exceed the ±20 V V_GS absolute maximum - even a brief overshoot from a mis-tuned gate-drive resistor can destroy the gate oxide. Add a 10 kΩ gate-to-source pull-down resistor to hold the FET off during controller startup, and place a 10 V Zener (e.g. BZX84C10) gate clamp if the gate-drive supply exceeds 18 V. The Source-Down package is NOT a drop-in for a standard PQFN - verify the land pattern against the Infineon PG-WHSON-8-1 reference before board rework.
Compliance Information
RoHS and lead-free status confirmed via Infineon product page. AEC-Q100 qualification not stated in the verified data; check with Infineon for automotive-grade Source-Down variants if required. Halogen-free status not explicitly listed in verified data.
