TPS53681RSBT - 6+2/5+3 D-CAP+ Multiphase Controller | Texas Instruments
MPN: TPS53681RSBT ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.91 | $12.91 |
| 10 | $11.78 | $117.80 |
| 100 | $10.42 | $1,042.00 |
| 500 | $9.35 | $4,675.00 |
| 1,000 | $8.2 | $8,200.00 |
TPS53681RSBT Overview
A step-down (buck) controller is a switch-mode power supply (SMPS) control IC that drives external MOSFETs or smart power stages to convert a higher DC input voltage into a lower regulated DC output voltage. A multiphase buck controller interleaves multiple converter phases to share the load current, reduce input/output ripple, and improve thermal distribution across the PCB. The TPS53681RSBT sits at the top of the power-management hierarchy: buck controller -> DC-DC controller -> power management IC (PMIC) -> semiconductor device.
Key features include dual-channel operation configurable as 6+2 phases or 5+3 phases, TI D-CAP+ control architecture for fast transient response without external compensation, full PMBus 1.3.1 compliance for telemetry and programmability, integrated NVM for storing default configuration, and pin compatibility with TI NexFET smart power stages such as CSD95490 and CSD95492. The device operates from a 4.5 V to 28 V main supply and supports output voltages from 0.25 V to 5 V.
The D-CAP+ architecture uses an internal ripple injection network and adaptive on-time control, eliminating the external compensation components required by traditional peak-current-mode controllers. Combined with TI NexFET power stages, the TPS53681RSBT achieves high efficiency from sub-ampere sleep states to multi-hundred-ampere peak loads typical in Intel VR13 and AMD SVI2 server rails.
Typical applications include server CPU core rails, DDR4/DDR5 VTT termination, high-end workstation and gaming-rig CPU/GPU power, base-station DSPs, and PCIe card auxiliary power. PMBus telemetry and fault logging make the part well suited to data-center PSUs and infrastructure platforms where remote monitoring is mandatory.
When designing with this part, place decoupling capacitors within 2 mm of each PVCC/VCIN pin and follow TI NexFET layout guidelines for gate-drive return paths. Always configure NVM defaults using TI's Fusion Digital Power Designer GUI before production ramp; mismatched PMBus addresses on parallel controllers can cause SMBus arbitration failures at start-up.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single source for sourcing, replacement, and application guidance.
Drop-in alternatives for TPS53681RSBT — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with TPS53681RSBT (same form factor and footprint) — differing in Package, Topology, Operating Temperature, Input Voltage Range, Number of Outputs.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
TPS53622RSBT
✅ Drop-In✓ In Stock
$3.96 / Unit
View Datasheet →TPS53681RSBR
✅ Drop-In📋 Reference alternative (not in catalog)
TPS53915RVER
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3.48 / Unit
View Datasheet →TPS53624
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$1.86 / Unit
View Datasheet →TPS536C9TRSLR
✅ Drop-In ⚠️ 参数待验证✓ In Stock
Contact for price
View Datasheet →TPS53681RSBT Maximum Ratings & Electrical Characteristics
| Topology | Dual-channel multiphase synchronous buck controller |
| Phase Configuration | 6+2 or 5+3 phases |
| Control Architecture | D-CAP+ adaptive on-time |
| Input Voltage Range | 4.5 V to 28 V |
| Output Voltage Range | 0.25 V to 5 V |
| Number of Outputs | 2 channels |
| Digital Interface | PMBus 1.3.1 compliant |
| On-Chip Memory | Non-volatile memory (NVM) |
| Compatible Power Stage | TI NexFET smart power stage |
| Package | WQFN-40 (RSB) 5x5 mm |
| Pin Count | 40 |
| Operating Temperature | -40 C to +125 C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead Finish | NiPdAu (lead-free) |
TPS53681RSBT Pin Configuration
| Pin 1 | VOUT1 — Channel 1 output voltage sense |
| Pin 2 | FB1 — Channel 1 feedback input |
| Pin 3 | VSNS1_P — Channel 1 positive voltage sense |
| Pin 4 | VSNS1_N — Channel 1 negative voltage sense return |
| Pin 5 | BST1A — Channel 1 phase A bootstrap |
| Pin 6 | PWM1A — Channel 1 phase A gate drive output |
| Pin 7 | PWM1B — Channel 1 phase B gate drive output |
| Pin 8 | BST1B — Channel 1 phase B bootstrap |
| Pin 9 | PWM1C — Channel 1 phase C gate drive output |
| Pin 10 | PWM1D — Channel 1 phase D gate drive output |
| Pin 11 | PWM1E — Channel 1 phase E gate drive output |
| Pin 12 | PWM1F — Channel 1 phase F gate drive output |
| Pin 13 | GND — Power ground |
| Pin 14 | PVCC — Power stage gate drive supply |
| Pin 15 | VCIN — Main input voltage sense |
| Pin 16 | EN — Enable (active high) |
| Pin 17 | PGOOD — Power good indicator (open-drain) |
| Pin 18 | FAULT — Fault output (open-drain) |
| Pin 19 | SDA — PMBus serial data |
| Pin 20 | SCL — PMBus serial clock |
| Pin 21 | ADDR — PMBus address select |
| Pin 22 | SYNC — Clock sync input/output |
| Pin 23 | V3P3 — 3.3V analog supply |
| Pin 24 | AGND — Analog ground |
| Pin 25 | REF — Internal reference bypass |
| Pin 26 | PWM2A — Channel 2 phase A gate drive output |
| Pin 27 | BST2A — Channel 2 phase A bootstrap |
| Pin 28 | PWM2B — Channel 2 phase B gate drive output |
| Pin 29 | BST2B — Channel 2 phase B bootstrap |
| Pin 30 | PWM2C — Channel 2 phase C gate drive output |
| Pin 31 | BST2C — Channel 2 phase C bootstrap |
| Pin 32 | VSNS2_N — Channel 2 negative voltage sense return |
| Pin 33 | VSNS2_P — Channel 2 positive voltage sense |
| Pin 34 | FB2 — Channel 2 feedback input |
| Pin 35 | VOUT2 — Channel 2 output voltage sense |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | PAD — Exposed thermal pad (GND) |
Typical Applications
TPS53681RSBT is suitable for 7 applications: Server CPU Core Rail (Intel VR13/AMD SVI2), DDR4/DDR5 Memory VTT Termination, High-End Workstation and Gaming-Rig CPU Power, Base-Station DSP and FPGA Core Rails, PCIe Card Auxiliary Power, Data-Center PSU and Infrastructure Platforms, Industrial High-Power Embedded Computing.
Server CPU Core Rail (Intel VR13/AMD SVI2)
The TPS53681RSBT's 6+2/5+3 multiphase topology and 0.25V minimum output deliver the >200 A peak currents demanded by Intel VR13 and AMD SVI2 server CPU core rails. D-CAP+ adaptive on-time control provides sub-microsecond transient response to load steps without external compensation. PMBus 1.3.1 telemetry reports voltage, current, and temperature per the platform VR13.1 telemetry spec.
Recommended
DDR4/DDR5 Memory VTT Termination
Using one channel in 2-phase mode, the TPS53681RSBT generates the 0.6 V VTT termination rail for DDR4/DDR5 memory with tight +/-1% voltage regulation and excellent load-transient response. D-CAP+ maintains regulation under the high di/dt of memory read/write bursts. PMBus monitoring lets the BMC track VTT current and over-temperature conditions in data-center DIMM arrays.
Recommended
High-End Workstation and Gaming-Rig CPU Power
The 6+2 phase configuration drives the CPU Vcore rail of enthusiast desktop and workstation platforms with currents up to ~250 A. The TPS53681RSBT's adaptive on-time D-CAP+ control eliminates external compensation components, simplifying PCB layout. PMBus programmability lets system integrators tune AVS profiles per SKU without resistor-divider changes on the motherboard.
Recommended
Base-Station DSP and FPGA Core Rails
The TPS53681RSBT powers TI KeyStone and other high-performance DSPs as well as FPGA core rails in 5G/4G base stations where multiphase efficiency and PMBus telemetry are both required. The 4.5 V to 28 V input range accepts -48 V telecom bus after an intermediate front-end converter. NVM stores per-platform default configurations, enabling fast board bring-up at the contract manufacturer.
Recommended
PCIe Card Auxiliary Power
GPU and accelerator PCIe cards use the TPS53681RSBT in 5+3 phase mode to deliver 12 V input to sub-1 V core rails at >100 A with PMBus telemetry reporting back through the host BMC. The 40-pin WQFN footprint fits within standard PCIe x16 card height constraints. D-CAP+ loop response handles GPU boost-state load steps that can swing by >150 A in <10 microseconds.
Recommended
Data-Center PSU and Infrastructure Platforms
The TPS53681RSBT's PMBus 1.3.1 fault logging and on-chip NVM make it a strong fit for redundant data-center PSU and infrastructure platforms where remote monitoring is mandatory. Integrated NVM stores black-box fault records that the BMC can retrieve after a fault event. The wide 4.5 V to 28 V input range simplifies integration into both 12 V and 24 V intermediate-bus architectures.
Recommended
Industrial High-Power Embedded Computing
Industrial servers and ruggedized embedded computing platforms use the TPS53681RSBT to power x86 or ARM SoC cores from a 24 V industrial bus. The -40 C to +125 C operating range supports outdoor cabinet and factory-floor deployments. PMBus telemetry enables predictive maintenance by reporting per-rail temperature trends over the platform's lifecycle.
Recommended
Recommended Products Summary
Engineering reference data for TPS53681RSBT — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | TPS53622RSBT | TPS53681RSBR | TPS53624 | TPS53915RVER | TPS536C9TRSLR |
|---|---|---|---|---|---|---|
| Package | WQFN-40 (RSB) 5x5 mm | WQFN-40 (RSB) 5x5 mm - same | WQFN-40 (RSB) 5x5 mm - same | WQFN-40 - same family | VQFN-40 - close family | VQFN-40 - close family |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Phase Configuration | 6+2 / 5+3 phases | 4+0 phases | 6+2 / 5+3 phases (same) | 4+1 / 3+2 phases | 4 phases single channel | 7+0 / 6+1 phases |
| Control Architecture | D-CAP+ | D-CAP+ | D-CAP+ (same) | D-CAP+ | D-CAP+ | AVSBus |
| Digital Interface | PMBus 1.3.1 | PMBus 1.3.1 | PMBus 1.3.1 (same) | PMBus 1.3.1 | PMBus 1.3.1 | AVSBus |
| On-Chip NVM | Yes | Yes | Yes (same) | Yes | Yes | Yes |
| Input Voltage Range | 4.5 V to 28 V | 4.5 V to 28 V | 4.5 V to 28 V (same) | 4.5 V to 28 V | 4.5 V to 28 V | 4.5 V to 28 V |
| Output Voltage Range | 0.25 V to 5 V | 0.25 V to 5 V | 0.25 V to 5 V (same) | 0.25 V to 5 V | 0.25 V to 5.5 V | 0.25 V to 5 V |
| Operating Temperature | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C (same) | -40 C to +125 C | -40 C to +125 C | -40 C to +125 C |
Key Differentiators
- Highest phase count in TI's PMBus 1.3.1 D-CAP+ family (vs TPS53624)
- Dual-channel PMBus with on-chip NVM (vs TPS53915RVER)
- Lower-cost tape and reel option (vs TPS53681RSBR)
- Mature D-CAP+ ecosystem versus newer AVSBus (vs TPS536C9TRSLR)
Design Notes
Place the 4.7 uF V3P3 analog bypass and the 1 uF PVCC gate-drive decoupling capacitors within 2 mm of their respective pins. Route the SYNC/SDA/SCL traces as a 50 ohm microstrip with ground-reference and keep them away from the BST1A/BST2A boost-switching nodes to avoid PMBus CRC errors at high di/dt. The exposed thermal pad must be soldered to a continuous ground plane with at least 9 thermal vias (0.3 mm drill) for a theta_JA below 30 C/W.
Estimated: at full load the TPS53681RSBT itself dissipates approximately 1.5 W due to gate-charge losses driving six NexFET power stages; the overall board thermal budget is dominated by the NexFET stages (CSD95490 loses ~6 W each at 60 A). For a 6-phase CPU rail at 250 A peak, total NexFET losses reach ~36 W and demand at least 4 square inches of inner-layer copper pour for heat-spreading.
Mismatched PMBus addresses between two paralleled TPS53681RSBT controllers cause SMBus arbitration failures during NVM auto-load at start-up. The ADDR pin strap (GND, 10 k, 22 k, 47 k to V3P3) sets the 7-bit address; always verify with the Fusion Digital Power Designer GUI before production ramp. Also, do not skip the BST diode/ capacitor network per phase, or the high-side MOSFET will not turn on and the rail will fail to regulate above 50% duty cycle.
Follow TI NexFET smart power stage layout guidelines: keep the high-side/low-side gate-loop area below 0.5 square cm and route the BOOT-node return directly to the phase-node pin on the power stage. Use a 4-layer PCB with a continuous ground plane on layer 2 to keep switching-node EMI below CISPR 22 Class B limits without common-mode chokes.
Compliance Information
RoHS and REACH compliant per TI product page. Standard TPS53681RSBT is not AEC-Q100 qualified; for automotive-grade multiphase controllers refer to TI's TPS536xx-Q1 family. Lead-free NiPdAu finish.
