TPS54120 - Low-Noise 1A Buck + LDO Power Supply | TI
MPN: TPS54120 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.2 | $5.20 |
| 10 | $4.68 | $46.80 |
| 100 | $4.16 | $416.00 |
| 500 | $3.75 | $1,875.00 |
| 1,000 | $3.35 | $3,350.00 |
Drop-in alternatives for TPS54120 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
TPS54120RGYT
β Drop-Inπ Reference alternative (not in catalog)
TPS54120 Maximum Ratings & Electrical Characteristics
| Function | Step-down (buck) DC-DC converter + linear (LDO) regulator, dual output |
| Output Current | 1 A |
| Switching Frequency Range | 200 kHz to 1.2 MHz |
| Frequency Synchronization | Yes |
| Soft-Start | Adjustable |
| Power Good Output | Yes |
| Overcurrent Protection | Yes |
| UVLO | Fixed |
| Output Discharge | Yes |
| Package | VQFN-24 (RGY) 5.5 x 3.5 mm |
| Mounting Type | Surface Mount |
TPS54120 Pin Configuration
| Pin 1 | PVIN β Buck power stage input supply |
| Pin 3 | EN β Enable input |
| Pin 5 | SS/TR β Soft-start / tracking adjust |
| Pin 6 | RT/CLK β Switching frequency set / sync input |
| Pin 8 | BOOT β High-side gate driver bootstrap |
| Pin 10 | PH β Buck switch node (inductor connection) |
| Pin 13 | PGND β Power ground |
| Pin 15 | VSENSE β Buck feedback voltage sense |
| Pin 17 | LDOIN β LDO input (from buck output) |
| Pin 19 | LDOOUT β LDO regulated output |
| Pin 20 | FB β LDO feedback |
| Pin 22 | PWRGD β Power good open-drain output |
| Pin 24 | AGND β Analog ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
TPS54120 is suitable for 6 applications: Telecom Infrastructure Power, Pico and Femto Base Station Clocking Power, Sensitive Clocking Distribution, RF and PLL Power Rails, Precision Analog and Data Converter Supplies, Compact Point-of-Load Modules.
Telecom Infrastructure Power
The TPS54120 fits telecom infrastructure rails that must combine efficiency with low output noise. The integrated buck stage converts the intermediate bus at 200 kHz to 1.2 MHz (synchronizable to a system clock), while the high-PSR LDO stage removes switching ripple before the load. This two-stage integration in a single 24-pin VQFN reduces board area and BOM count versus a discrete converter-plus-LDO chain, and the power-good flag supports rail supervision in multi-supply line cards.
Recommended
Pico and Femto Base Station Clocking Power
Small-cell base stations need compact, clean supplies for PLL and synthesizer circuits. The TPS54120's LDO stage provides high power-supply rejection that suppresses buck ripple, keeping clock phase noise low. The adjustable soft-start controls inrush in power-limited small-cell designs, and frequency synchronization prevents beat frequencies between multiple supplies. Per the TI datasheet, this is a primary named application for the device.
Recommended
Sensitive Clocking Distribution
Jitter attenuators, clock trees, and distribution buffers are highly sensitive to supply noise; even millivolts of ripple can raise phase jitter. The TPS54120 delivers a 1-A low-noise rail by filtering the buck output through its integrated LDO, achieving noise far below a buck-only solution. Using the sync pin locks its switching frequency away from sensitive clock harmonics, and output discharge helps controlled power-down in clock modules.
Recommended
RF and PLL Power Rails
RF synthesizers and PLLs demand supply noise well below typical buck output ripple. The TPS54120's cascaded buck-plus-LDO topology provides high power-supply rejection in one package, so designers avoid a separate LDO IC. Place the device close to the PLL with local output capacitance; the LDO headroom of a few hundred millivolts is sufficient to maintain rejection while keeping dissipation low at 1-A loads.
Recommended
Precision Analog and Data Converter Supplies
High-resolution ADCs and precision amplifiers benefit from low-noise analog supplies. The TPS54120 supplies up to 1 A at ultra-low noise, enough for converter analog rails and reference buffers. The buck stage keeps efficiency high so the final LDO stage dissipates only the headroom delta, and the power-good output allows the system to gate data-converter calibration until supplies are stable.
Recommended
Compact Point-of-Load Modules
Space-constrained boards gain from integrating two regulation stages in one 5.5 x 3.5 mm VQFN-24 package. The TPS54120 replaces a discrete buck plus LDO pair, cutting component count and assembly cost while improving ripple rejection through short internal interconnect. The 200 kHz to 1.2 MHz range allows smaller magnetics at the high-frequency end, supporting dense point-of-load designs in industrial and networking equipment.
Recommended
Recommended Products Summary
Engineering reference data for TPS54120 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | TPS54120RGYT | TPS62912 |
|---|---|---|---|
| Package | VQFN-24 (RGY) 5.5x3.5 mm | VQFN-24 (RGY) - same | [DATA_NEEDED: package] |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments |
| Output Current | 1 A | 1 A | 1 A |
| Architecture | Buck + LDO (two-stage, low noise) | Buck + LDO - same | Buck only |
| Switching Frequency | 200 kHz to 1.2 MHz, syncable | 200 kHz to 1.2 MHz | [DATA_NEEDED: switching frequency] |
| Frequency Synchronization | Yes | Yes | Yes |
| Spread-Spectrum Clocking | No | No | Yes |
| Power Good Output | Yes | Yes | Yes |
| Integrated LDO Stage | Yes (high PSR) | Yes | No |
Key Differentiators
- Integrated high-PSR LDO second stage (vs TPS62912)
- Two-stage integration saves board area (vs Discrete buck + LDO (e.g., TPS54620 + TPS7A4701))
- Wide synchronizable frequency range (vs TPS62912)
Design Notes
Keep the buck hot loop (PVIN input capacitor, BOOT capacitor, PH switch node, PGND) as compact as possible on the top layer; place the inductor within 2-3 mm of the PH pins. Solder the VQFN exposed thermal pad to a grounded copper pour with an array of vias to dissipate heat from both the buck and LDO stages. Follow the TI datasheet layout example for the RGY footprint.
Set the buck output a few hundred millivolts above the desired LDO output so the LDO stays in regulation and maintains power-supply rejection. Too little headroom degrades ripple rejection; too much increases LDO dissipation (P = (V_LDOIN - V_LDOOUT) x I_OUT). At 1 A, budget each extra volt of headroom as 1 W of additional loss in the thermal design.
Use the RT/CLK synchronization feature to lock the switching frequency away from sensitive analog or RF clock harmonics in clocking-distribution systems. Synchronizing multiple TPS54120 instances to a common clock prevents beat-frequency products in multi-rail boards. Slow the frequency toward 200 kHz for higher efficiency, or toward 1.2 MHz for smaller inductors and faster transient response.
Do not omit the soft-start capacitor; without it, inrush current can trip the overcurrent protection during startup into large output capacitance. Route the VSENSE feedback trace away from the PH switch node to avoid noise injection, and use the PWRGD output to hold downstream loads off until the rail is valid.
Compliance Information
Compliance data not present in provided verified web data; confirm on TI product page quality/environmental section for TPS54120RGYT/RGYR ordering PN.
