10AX115H3F34I2LG - Arria 10 GX 1.15M LEs FPGA | Intel FPGA
MPN: 10AX115H3F34I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8491.57 | $8,491.57 |
| 5 | $8050 | $40,250.00 |
| 10 | $7750 | $77,500.00 |
| 25 | $7350 | $183,750.00 |
| 100 | $6800 | $680,000.00 |
Drop-in alternatives for 10AX115H3F34I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX115H3F34E2LG
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View Datasheet →10AX115H2F34I2LG
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View Datasheet →10AX115H2F34I2SG
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View Datasheet →10AX115H1F34I1SG
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View Datasheet →10AX115H1F34E1SG
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View Datasheet →10AX115H3F34I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LEs) | 1,150,000 |
| Embedded Memory | 68,857,856 bits |
| User I/O Count | 504 |
| Transceiver Count | 24 |
| Maximum Transceiver Data Rate | 17.4 Gbps |
| DSP Blocks | Variable-precision, floating-point capable |
| DSP Performance | Up to 1.5 TFLOP/s (FP) |
| Hardened Memory Controllers | DDR4/DDR3/LPDDR3 |
| Hardened PCIe | PCIe Gen3 x8 |
| Hardened Ethernet MAC | 10G/40G/100G capable |
| Core Voltage | 0.9 V |
| Process Node | 20 nm |
| Package | 1152-ball FCBGA |
| Speed Grade | H3 |
| Temperature Grade | Industrial (-40C to +100C junction) |
| RoHS Status | Compliant |
10AX115H3F34I2LG 1152-ball fcbga Pin Configuration Guide
Complete pinout information for 10AX115H3F34I2LG (1152-ball fcbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115H3F34I2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115H3F34I2LG is suitable for 6 applications: 4K/8K Video Broadcast Equipment, Radar and Electronic Warfare Signal Processing, Medical Imaging Backplanes, High-Speed Protocol Test and Measurement, High-Bandwidth Data Center Acceleration, Industrial Machine Vision and Inspection.
4K/8K Video Broadcast Equipment
The 10AX115H3F34I2LG's 1.15M logic elements, 504 user I/O, and 24 transceivers at up to 17.4 Gbps make it ideal for 4K/8K video processing and broadcast infrastructure. The device's hard PCI Express Gen3 x8 block and 10/40G Ethernet MAC enable direct interfacing with camera links, SDI-to-IP gateways, and uncompressed video pipelines. Per Intel Arria 10 documentation, the FPGA's variable-precision DSP blocks deliver up to 1.5 TFLOP/s, sufficient for real-time HEVC/H.265 encode/decode of 4Kp60 streams at multiple channels. The 68.85 Mbits of embedded memory serves as line/frame buffers, while the 504 I/O handle multiple parallel SDI inputs without external muxing. Placed on a video capture card, it ingests 12G-SDI quad-link, performs color space conversion, and outputs SMPTE ST 2110 over 25G Ethernet.
Recommended
Radar and Electronic Warfare Signal Processing
The 10AX115H3F34I2LG's variable-precision DSP blocks (up to 1.5 TFLOP/s floating-point) and 17.4 Gbps transceivers suit radar, electronic warfare (EW), and signal-intelligence systems. Each transceiver digitizes a wideband antenna channel into the FPGA where pulse compression, MTI filtering, and STAP algorithms run in real time. With 24 transceivers, the device handles multi-channel phased-array antennas directly. Per Intel application notes, Arria 10 GX devices support JESD204B/C interfaces to modern ADC/DAC converters - critical for direct RF sampling. The industrial temperature grade (-40C to +100C junction) meets MIL-STD-810 environmental needs when paired with conformal coating. The hardened DDR4 controller attaches directly to high-bandwidth capture memory, eliminating external bridge chips.
Recommended
Medical Imaging Backplanes
The 10AX115H3F34I2LG fits medical imaging systems such as CT scanners, MRI receive chains, and ultrasound beamformers. Its 24 transceivers aggregate data from dozens of analog front-end channels, while the hardened DDR4 controller interfaces to high-capacity image buffers. The variable-precision DSP blocks accelerate backprojection, FFT, and beamforming kernels. Per the Intel Arria 10 datasheet family, the industrial temperature grade suits the controlled thermal environment of imaging carts. The FPGA's low-latency transceiver pipeline keeps total deterministic latency under 1 microsecond end-to-end, which is essential for synchronization between modalities. IEC 60601-1 compliance is achieved at the system level via isolation barriers - the FPGA sits on the patient-isolated side.
Recommended
High-Speed Protocol Test and Measurement
The 10AX115H3F34I2LG is ideal for high-end protocol analyzers, BERT (bit-error-rate testers), and compliance test platforms supporting PCIe Gen3, 10G/40G/100G Ethernet, CPRI, and Interlaken. Its hardened PCIe Gen3 x8 and 10G/40G/100G Ethernet MAC blocks eliminate soft-IP resource consumption, leaving maximum fabric available for pattern generation and error counting. The 17.4 Gbps transceivers support next-gen 25G/50G Ethernet and 32G Fibre Channel. Per Intel documentation, the H3 speed grade guarantees timing closure at the highest transceiver data rates. Test-and-measurement OEMs value the device's deterministic latency and signal-integrity margin for producing repeatable measurements.
Recommended
High-Bandwidth Data Center Acceleration
The 10AX115H3F34I2LG serves as a hardware accelerator in data center NICs, NVMe-over-Fabrics targets, and storage controllers. Its PCIe Gen3 x8 hard IP enables single-root I/O virtualization (SR-IOV) without taxing fabric resources, while the 68.85 Mbits of embedded memory accelerates lookup tables and flow caches. The 17.4 Gbps transceivers support 25G/50G Ethernet NICs and 100G aggregation. Per Intel, Arria 10 devices are widely deployed in hyperscaler hardware acceleration cards because of their low-power 20 nm process and hard IP that offloads routine functions from the fabric. The FPGA's industrial temperature grade suits edge deployment in non-climate-controlled server rooms.
Recommended
Industrial Machine Vision and Inspection
The 10AX115H3F34I2LG powers high-throughput machine vision systems used in semiconductor inspection, flat-panel display AOI (automated optical inspection), and high-speed sorting lines. Its 504 user I/O drive dozens of Camera Link, CoaXPress, or 10GigE Vision cameras in parallel, while the variable-precision DSP blocks accelerate image preprocessing, defect detection, and AI inference. Per Intel application notes, the device's hardened DDR4 controller sustains the multi-gigabyte-per-second bandwidth required for 4K line-scan cameras. The industrial temperature grade (-40C to +100C junction) supports factory-floor deployments with wide ambient swings. The 24 transceivers also support deterministic low-latency EtherCAT and PROFINET links to factory automation networks.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H3F34I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H3F34E2LG | 10AX115H2F34I2LG | 10AX115H2F34I2SG | 10AX115H1F34I1SG | 10AX115H1F34E1SG |
|---|---|---|---|---|---|---|
| Package | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Speed Grade | H3 (highest) | H3 | H2 (-1 step) | H2 (-1 step) | H1 (-2 steps) | H1 (-2 steps) |
| Max Transceiver Data Rate | 17.4 Gbps | 17.4 Gbps | 14.2 Gbps | 14.2 Gbps | 10 Gbps | 10 Gbps |
| Temperature Grade | Industrial (-40C to +100C junction) | Extended (E2) | Industrial | Industrial | Industrial | Extended |
| Lead-Free Finish | Leaded (LG) | Leaded (LG) | Leaded (LG) | Lead-free (SG) | Lead-free (SG) | Lead-free (SG) |
| RoHS Compliant | No (legacy leaded) | No | No | Yes | Yes | Yes |
| User I/O Count | 504 | 504 | 504 | 504 | 504 | 504 |
Key Differentiators
- Highest speed grade in the Arria 10 GX F34 family (vs 10AX115H2F34I2LG)
- Same footprint across the F34 family for transparent migration (vs 10AX115H1F34I1SG)
- No cross-brand drop-in exists - Arria 10 is Intel-exclusive (vs Cross-brand alternatives (Xilinx Kintex, Lattice ECP5))
Design Notes
The 1152-ball FCBGA F34 package uses 1.0 mm ball pitch on a 35 x 35 mm body. Per Intel PCB design guidelines for Arria 10, escape routing requires at least 4 PCB layers with microvia-in-pad or via-in-pad plating, and the top two signal layers must be microvia-routed to all inner balls. Matched-length impedance control is mandatory for transceiver channels: 100 ohm differential with intra-pair skew under 0.15 ps/mm. Place AC-coupling capacitors within 250 mil of the transceiver ball. Use a continuous reference plane beneath the FCBGA footprint; split planes at the BGA create resonance that corrupts high-speed signals.
Arria 10 FPGAs require a multi-rail power delivery network. Per Intel PowerPlay guidance, the device typically draws VCC (0.9V core), VCCPT (1.0V programmable technology), VCCAUX (1.8V auxiliary), VCCBAT (battery backup for key encryption), and per-bank VCCHIP and VCCIO supplies. The H3 speed grade at full transceiver utilization can draw 30+ watts transient. Use a sequencer (e.g., LTC2987 or dedicated PMIC like LTM4686) to enforce the required power-up/power-down order. Decoupling: place 0402 0.1uF X7R capacitors on every fourth VCC ball and bulk 22uF ceramic on each supply island within 200 mil of the BGA.
At full transceiver utilization the Arria 10 GX device can dissipate 25-35 W. The F34 FCBGA package has a published theta_JB of approximately 0.5 C/W and theta_JC of approximately 0.1 C/W. Per Intel thermal guidance, attaching a heatsink with thermal interface material (TIM) rated for at least 5 W/mK is mandatory for continuous full-load operation. In an air-cooled chassis, provide 200 LFM minimum airflow across the heatsink. For conduction-cooled applications, mount the BGA to a metal chassis plate through an opening in the PCB using a custom heatsink frame. Monitor junction temperature via the internal Arria 10 temperature sensor accessible through the System Console.
Do not assume any other 1152-ball FCBGA package is pin-compatible with the F34 - Intel uses different package codes (F34, F35, F40, F45) for Arria 10 across transceiver-count variants. The 10AX115H3F34I2LG must only be substituted with another F34 OPN. A common mistake is to migrate to the F45 (1932-ball FCBGA) variant on the assumption that 'more balls are always backward compatible' - they are NOT. Verify the F34 package code in the Intel ordering part number decoder before substituting. Also note that the leaded (LG) variant may not meet RoHS - choose the SG suffix for RoHS-compliant new designs.
Compliance Information
RoHS: NOT compliant because the LG suffix indicates leaded finish. For RoHS-compliant builds, choose the SG suffix variant (e.g., 10AX115H3F34I2SG). REACH and conflict-minerals compliance per Intel product stewardship statements. AEC-Q100 not applicable - FPGAs are not automotive-grade qualified per AEC-Q100; use automotive-qualified parts separately for that market.
