10CX105YF672I6G - Cyclone 10 GX FPGA, 105K LE, 672-BGA | Intel
MPN: 10CX105YF672I6G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $405 | $4,050.00 |
| 100 | $372 | $37,200.00 |
| 250 | $355 | $88,750.00 |
| 500 | $338 | $169,000.00 |
Drop-in alternatives for 10CX105YF672I6G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10CX105YF672I5G
✅ Drop-In✓ In Stock
$108 / Unit
View Datasheet →10CX105YF672E6G
✅ Drop-In✓ In Stock
$100.547 / Unit
View Datasheet →10CX105YF672E5G
✅ Drop-In✓ In Stock
$310 / Unit
View Datasheet →10CX085YF672I6G
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$255 / Unit
View Datasheet →10CX150YF672I5G
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$278.4 / Unit
View Datasheet →10CX105YF672I6G Maximum Ratings & Electrical Characteristics
| Series | Cyclone® 10 GX |
| Logic Elements (LE) | 104,000 |
| Adaptive Logic Modules (ALM) | 3,800 ALM |
| Embedded Memory | 7.46 Mbit |
| Embedded Memory Bits | 8,641,536 bits |
| Number of User I/Os | 236 |
| Package | 672-BBGA, FCBGA (F672) |
| Mounting Type | Surface Mount |
| Operating Supply Voltage (Core) | 900 mV |
| Operating Temperature | -40°C to +85°C (Industrial) |
| Temperature Grade | Industrial (I) |
| Speed Grade | 6 |
| Process Technology | TSMC 20 nm |
| Lead Free / RoHS | Yes (RoHS compliant) |
| Configuration Method | JTAG / AS / PS / FPP |
10CX105YF672I6G 672-bbga, fcbga (f672) Pin Configuration Guide
Complete pinout information for 10CX105YF672I6G (672-bbga, fcbga (f672) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX105YF672I6G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX105YF672I6G is suitable for 6 applications: Industrial Machine Vision, Video Broadcasting and Encoding, Factory Automation Controllers, 10 Gigabit Ethernet Aggregation, Software-Defined Radio Front-Ends, PCIe-Based Accelerator Cards.
Industrial Machine Vision
The 10CX105YF672I6G is well-suited for industrial machine vision systems requiring real-time image processing on multiple parallel video streams. With 104K logic elements, 3,800 ALMs, and 12 transceiver channels up to 12.5 Gbps, the FPGA can ingest data from MIPI CSI-2, Camera Link, or CoaXPress sensors while running pipeline-parallel image processing (filtering, blob detection, optical flow). The industrial -40°C to +85°C temperature grade allows deployment in factory floor enclosures without active thermal management beyond PCB copper. Its 236 user I/Os support multiple parallel sensor interfaces simultaneously, while the hard PCIe Gen2 x4 IP enables host-side data transfer with minimal CPU overhead. Compared to discrete GPU solutions, this FPGA offers deterministic latency critical for vision-based quality control in high-speed production lines.
Recommended
Video Broadcasting and Encoding
Broadcast video encoding applications (e.g., JPEG2000, H.264, HEVC mezzanine compression) benefit from the 10CX105YF672I6G's combination of logic density, DSP blocks, and serial transceiver channels. The 12 transceivers support SDI (3G/12G-SDI over coax), HDMI 2.0 bridging, or 10 Gigabit Ethernet for IP-based video transport. Hard PCIe Gen2 enables direct host offload in server-class encoders. The 105K LE fabric comfortably hosts multiple encoder cores, audio embedding, and ancillary data processing simultaneously. Industrial temperature rating supports operation in outdoor broadcast trucks and stadium control rooms. Power consumption is significantly lower than equivalent Stratix 10 implementations, fitting the cost-sensitive mid-tier of the broadcast equipment market where the 10CX105YF672I6G's price point is competitive.
Recommended
Factory Automation Controllers
Programmable logic controllers and industrial Ethernet gateways leverage the 10CX105YF672I6G to consolidate multiple industrial protocols (EtherCAT, PROFINET, EtherNet/IP) onto a single FPGA fabric. Its 104K logic elements can host multiple industrial slave stacks concurrently, while the 236 user I/Os handle real-time digital I/O, encoder feedback, and motor control PWM. The industrial -40°C to +85°C temperature grade is mandatory for factory cabinet deployment. The 12 transceiver channels support multiple GbE links or one 10G uplinks to supervisory networks. Compared to multi-chip solutions, this single FPGA reduces BOM count, simplifies firmware qualification, and provides deterministic sub-microsecond latency required for closed-loop servo control. The hard PCIe Gen2 IP also enables compact vision-in-the-loop and edge analytics integration.
Recommended
10 Gigabit Ethernet Aggregation
The 10CX105YF672I6G is ideal for low-cost 10 Gigabit Ethernet aggregation switches and protocol converters at the network edge. Its 12 transceiver channels support up to six 10G SFP+ uplinks or twelve 1G SFP ports with line-rate processing. The hard PCIe Gen2 x4 IP allows tight integration with host CPUs or SoCs in hybrid switching platforms. With 7.46 Mbit of embedded memory, the device can buffer multiple 10G line-rate streams while running MAC, VLAN, and basic ACL processing in fabric. Industrial temperature grade suits outdoor telecom cabinets and small-cell backhaul applications. The cost/performance point positions this FPGA between discrete PHY/MCU solutions and full merchant switch silicon, ideal for custom OEM networking equipment with mixed layer-2/3 functionality.
Recommended
Software-Defined Radio Front-Ends
Software-defined radio (SDR) platforms leverage the 10CX105YF672I6G's transceiver channels and DSP blocks for digital down-conversion, channelization, and baseband processing. The 12 transceivers up to 12.5 Gbps can digitize wide-band RF signals directly from high-speed ADCs, supporting LTE, 5G NR sub-6, and proprietary waveform protocols. The 104K logic elements host multiple DDC/DUC chains, channel filters, and FFT cores. Hard PCIe Gen2 x4 enables direct connection to host processors for protocol stack implementation. The industrial temperature grade supports outdoor SDR deployments (private LTE base stations, military communications, spectrum monitoring). Compared to dedicated DSP processors, this FPGA offers 5-10x higher sample-rate throughput at comparable power, while providing flexibility to support evolving waveforms.
Recommended
PCIe-Based Accelerator Cards
The 10CX105YF672I6G's hard PCIe Gen2 x4 IP makes it a strong choice for low-cost accelerator cards targeting financial computing, genomics, machine learning inference, and database acceleration. The 105K logic elements can host custom compute pipelines (e.g., Smith-Waterman alignment, AES encryption, neural-network inference engines) that offload work from host CPUs. The 12 transceivers support both the PCIe link and additional high-speed I/O to host (DMA) or to other cards (peer-to-peer). Industrial temperature rating supports server-room and edge data center deployment. Compared to GPU accelerators, this FPGA offers deterministic latency and significantly lower power per operation for fixed-function workloads. The 7.46 Mbit embedded memory is sufficient for caching intermediate results in streaming pipelines.
Recommended
Recommended Products Summary
Engineering reference data for 10CX105YF672I6G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX105YF672I5G | 10CX105YF672E6G | 10CX105YF672E5G | 10CX085YF672I6G | 10CX150YF672I5G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BBGA, FCBGA (F672) | 672-BBGA, FCBGA (F672) - same | 672-BBGA, FCBGA (F672) - same | 672-BBGA, FCBGA (F672) - same | 672-BBGA, FCBGA (F672) - same | 672-BBGA, FCBGA (F672) - same |
| Logic Elements | 104,000 LE | 104,000 LE - same | 104,000 LE - same | 104,000 LE - same | 85,000 LE (-19%) | 150,000 LE (+44%) |
| Speed Grade | -6 | -5 (faster) | -6 - same | -5 (faster) | -6 - same | -5 (faster) |
| Temperature Grade | Industrial (-40°C to +85°C) | Industrial - same | Enhanced (E) | Enhanced (E) | Industrial - same | Industrial - same |
| Embedded Memory | 7.46 Mbit | 7.46 Mbit - same | 7.46 Mbit - same | 7.46 Mbit - same | 6.62 Mbit | 8.47 Mbit |
| User I/Os | 236 | 236 - same | 236 - same | 236 - same | 236 - same | 236 - same |
| RoHS / Lead-Free | Yes (RoHS compliant) | Yes - same | Yes - same | Yes - same | Yes - same | Yes - same |
Key Differentiators
- Higher logic density than 10CX085 family variants (vs 10CX085YF672I6G)
- Industrial temperature grade at -6 speed grade (vs 10CX105YF672E6G)
- Lower cost than 10CX150 family variants (vs 10CX150YF672I5G)
Design Notes
The 672-ball FCBGA package requires a high-density PCB with 1.0 mm ball pitch and matched-impedance traces for the transceiver channels. Intel provides reference PCB stack-ups in the Cyclone 10 GX Hardware Reference Manual. Use 0.5 oz copper in the core and 1 oz on outer layers; 6-8 layer stack-up is recommended. Decoupling requires 10-22 μF bulk + 0.1 μF + 1 nF per power pin per Intel's pin connection guidelines.
Estimated: at typical Cyclone 10 GX utilization (60% LEs, 80% transceivers active), core power is approximately 4-6 W. The FCBGA package has a θJA of approximately 14-18 °C/W with adequate PCB thermal vias and copper pour. Industrial temperature design must keep junction below 85°C ambient; recommend 200-400 LFM airflow or large thermal copper pad with 25-50 thermal vias under the BGA.
Do not mix core and I/O power ramp sequences arbitrarily - Intel requires specific power sequencing (VCC core first, then VCCIO, then transceivers) per AN692. The MSEL[2:0] pins must be set correctly to select the configuration mode (JTAG/AS/PS/FPP) at board reset. Differential transceiver channels require DC-blocking capacitors and matched-length routing within 0.025 mm tolerance. Misconfigured MSEL or missing reference-clock termination is a common first-prototype failure.
Compliance Information
RoHS compliant per 'G' suffix in MPN. Lead-free FCBGA assembly. AEC-Q100 not applicable for FPGAs. Halogen-free status not confirmed in verified data - set to 'unknown'.
