10CX150YF672I5G - Cyclone 10 GX FPGA, 150K LE, 672-FCBGA | Intel
MPN: 10CX150YF672I5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $380.5 | $3,805.00 |
| 100 | $338.75 | $33,875.00 |
| 250 | $305.2 | $76,300.00 |
| 500 | $278.4 | $139,200.00 |
Drop-in alternatives for 10CX150YF672I5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →10CX150YF672I5G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 GX |
| Logic Elements | 150,000 |
| Adaptive Logic Modules (ALMs) | 54,770 |
| Embedded Memory | 10,907,648 bits (10.652 Mbit) |
| Number of I/Os | 236 |
| Package | 672-BBGA, FCBGA (27 mm x 27 mm, 1.0 mm pitch) |
| Operating Supply Voltage (Core) | 0.9 V |
| Operating Temperature | -40C to +100C (Industrial) |
| Mounting Style | SMD/SMT |
| Transceiver Data Rate | Up to 12.5 Gbps |
| PCI Express Hard IP | Gen2 (x1/x2/x4) |
| External Memory Interface | DDR3, DDR4, LPDDR3 hard controller |
| Multipliers | 156 (18 x 19) |
| Process Technology | 20 nm |
| RoHS Status | Compliant |
10CX150YF672I5G 672-bbga, fcbga (27 mm x 27 mm, 1.0 mm pitch) Pin Configuration Guide
Complete pinout information for 10CX150YF672I5G (672-bbga, fcbga (27 mm x 27 mm, 1.0 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX150YF672I5G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX150YF672I5G is suitable for 6 applications: Industrial Machine Vision Frame Grabber, 10 Gigabit Ethernet Aggregation Switch Line Card, Wireless Fronthaul CPRI 4.9G / 9.8G Radio Unit, Video Broadcast Routing and Processing, Low-Latency Financial Trading Appliance, Automotive Sensor Aggregation ECU.
Industrial Machine Vision Frame Grabber
The 10CX150YF672I5G's 12.5 Gbps transceivers and PCIe Gen2 x4 hard IP make it ideal for industrial machine vision frame grabbers that aggregate multiple CoaXPress or Camera Link HS camera streams. The 150 K logic elements, 156 18x19 multipliers, and 10.65 Mbit embedded memory support real-time image preprocessing (tap balancing, gamma correction, defect pixel replacement) before DMA transfer to host CPU via PCIe Gen2. The industrial -40C to +100C temperature range enables deployment on factory floors without thermal screening. Place the FPGA on a host PCIe card with a 4-lane Gen2 edge connector; a SFP+ cage connects to remote cameras over fiber up to 10 km. Estimated fabric utilization for a 4-channel CoaXPress 1.1 frame grabber: 65-80% of 150 K LE.
Recommended
10 Gigabit Ethernet Aggregation Switch Line Card
The 10CX150YF672I5G integrates four 12.5 Gbps transceivers that can be configured as four 10 GbE SFP+ ports with hardware 10G MAC IP, making it suitable for top-of-rack aggregation line cards in cost-sensitive data center switches. The hard PCIe Gen2 x4 controller provides an out-of-band management plane to the switch CPU complex. According to Intel Cyclone 10 GX documentation, the 10G Ethernet MAC hard IP achieves line-rate performance with minimal fabric utilization. Industrial temperature grade supports thermally constrained rack environments. Place a heatsink on the FCBGA's exposed die region; airflow of 200 LFM minimum is recommended for full transceiver operation.
Recommended
Wireless Fronthaul CPRI 4.9G / 9.8G Radio Unit
The 10CX150YF672I5G's 12.5 Gbps transceivers and 150 K logic elements support CPRI 4.9G and 9.8G links between baseband units (BBU) and remote radio heads (RRH) in 4G LTE and 5G NR small-cell deployments. The hard PCIe Gen2 controller interfaces to a baseband SoC, while CPRI soft IP (CPRI v7.0) consumes roughly 25 K LE per link with scrambling, IQ data buffering, and control plane management. Industrial temperature grade supports outdoor radio unit enclosures without active cooling. A single 10CX150YF672I5G can handle up to three CPRI 9.8G links plus a 10 GbE backhaul, total fabric utilization approximately 70-85%.
Recommended
Video Broadcast Routing and Processing
The 10CX150YF672I5G serves in broadcast video routers and format converters supporting 12G-SDI, 3G-SDI, and HDMI 2.0 streams. The 12.5 Gbps transceivers can deserialize 12G-SDI (11.88 Gbps) with margin, while the 156 18x19 multipliers enable real-time color space conversion (REC.709 to REC.2020) and HDR tone mapping. The 10.65 Mbit embedded memory buffers multiple video frames for genlock and frame synchronization across async sources. Designers can implement a 4x4 12G-SDI router with on-screen display overlay using approximately 90% of available logic and 60% of embedded memory.
Recommended
Low-Latency Financial Trading Appliance
The 10CX150YF672I5G delivers sub-microsecond packet processing latency required for high-frequency trading (HFT) appliances. The 12.5 Gbps transceivers interface to 10 GbE market data feeds, while the FPGA fabric implements wire-speed parsing of ITCH, FIX, and FAST protocols plus pre-trade risk checks. According to Intel documentation, Cyclone 10 GX hard IP MAC plus soft parser achieves deterministic <500 ns latency from PHY to application logic. Industrial temperature grade supports colocation data centers. A 4x10G feed handler with order book management typically uses 80-110 K LE, fitting within the 150 K fabric with margin for additional analytics.
Recommended
Automotive Sensor Aggregation ECU
The 10CX150YF672I5G aggregates multiple automotive sensors (cameras, radar, lidar) in advanced driver assistance systems (ADAS) sensor ECUs. The 12.5 Gbps transceivers interface to automotive Ethernet (1000BASE-T1, 100BASE-T1) and FPD-Link III deserializers, while the PCIe Gen2 hard IP connects to the central ADAS SoC. The 150 K logic elements support sensor fusion preprocessing (object detection, lane marking, free-space computation) before forwarding to the central processor. While the industrial temperature grade (-40C to +100C) covers most automotive cabin deployments, AEC-Q100 qualified variants like 10CX220YF672I7G may be required for safety-critical ADAS functions. Fabric utilization for a 4-camera + 1 radar sensor ECU: approximately 95-120 K LE.
Recommended
Recommended Products Summary
Engineering reference data for 10CX150YF672I5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX105YF672I5G | 10CX150YF672E5G | 10CX105YF672I6G | 10CX150YF672E6G | 10CX105YF780E6G |
|---|---|---|---|---|---|---|
| Package | 672-FCBGA | 672-FCBGA (same) | 672-FCBGA (same) | 672-FCBGA (same) | 672-FCBGA (same) | 780-FCBGA (different package) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 150,000 | 105,000 (-30%) | 150,000 (same) | 105,000 (-30%) | 150,000 (same) | 105,000 (-30%) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (same) | Commercial (0C to +85C) | Industrial (same) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Speed Grade | 5 | 5 (same) | 5 (same) | 6 (slower) | 6 (slower) | 6 (slower) |
| Transceiver Data Rate | Up to 12.5 Gbps | Up to 12.5 Gbps (same) | Up to 12.5 Gbps (same) | Up to 12.5 Gbps (same) | Up to 12.5 Gbps (same) | Up to 12.5 Gbps (same) |
| Embedded Memory | 10,907,648 bits | [DATA_NEEDED] | 10,907,648 bits (same) | [DATA_NEEDED] | 10,907,648 bits (same) | [DATA_NEEDED] |
| Core Voltage | 0.9 V | 0.9 V (same) | 0.9 V (same) | 0.9 V (same) | 0.9 V (same) | 0.9 V (same) |
Key Differentiators
- Highest LE count among 672-FCBGA Cyclone 10 GX industrial variants (vs 10CX105YF672I5G)
- Industrial temperature grade for harsh environment deployment (vs 10CX150YF672E5G)
- Faster speed grade 5 for timing-critical designs (vs 10CX150YF672I6G)
Design Notes
Estimated: The 672-FCBGA package measures 27 mm x 27 mm with a 1.0 mm ball pitch, requiring a high-density interconnect (HDI) PCB stack-up with micro-via technology. Follow Intel's Cyclone 10 GX PCB design guidelines for impedance-controlled transceiver channels (100 ohm differential for 10 GbE, 85 ohm for CPRI). Use a minimum 8-layer stack-up with dedicated ground and power planes adjacent to the BGA breakout layer. Decoupling requirements per the manufacturer pin connection guidelines specify bulk, mid-frequency, and high-frequency decoupling capacitors placed within 100 mils of the BGA balls.
Estimated: At maximum transceiver utilization (all transceivers active at 12.5 Gbps) plus 80% fabric utilization, the 10CX150YF672I5G may dissipate 4-6 W depending on toggle rate. The 672-FCBGA package relies on the PCB for heat dissipation - no integrated heatsink. Design with a thermal pad area on the top PCB layer covering the die region, connected via thermal vias to internal ground planes. For enclosed systems, provide minimum 200 LFM airflow or attach an external heatsink with thermal interface material rated for the industrial temperature range.
Route high-speed transceiver channels with continuous reference planes (ground) on the layer immediately below. Maintain maximum trace length matching of 5 mils within a transceiver pair and across TX/RX pairs feeding the same protocol. For PCIe Gen2 x4 hard IP, route all four lanes on the same PCB layer with matched lengths; avoid vias in the transceiver channel path. JTAG and AS configuration pins (TCK, TMS, TDI, TDO, nCONFIG, nSTATUS, CONF_DONE, MSEL[4:0]) require careful placement near board edges for in-system programming access. Place the configuration flash (EPCS or compatible) within 2 inches of the FPGA for reliable AS mode boot.
Cyclone 10 GX transceivers require AC-coupled connections with 100 nF capacitors on both TX and RX pairs for protocols above 3 Gbps. For CPRI 4.9G and 9.8G, follow the JESD204B/EIA-364-1000 specification for connector and cable selection. Reference clocks must meet the transceiver reference clock jitter specification (typically <300 fs RMS jitter for 12.5 Gbps operation); use a dedicated low-jitter oscillator such as the SiTime SiT9102 or equivalent. Verify signal integrity with post-layout IBIS-AMI simulation using Intel's Quartus Prime SignalTap or external tools like Ansys HFSS.
Critical pitfalls to avoid: (1) Do not enable all 12.5 Gbps transceivers simultaneously without adequate thermal design - peak power exceeds typical operating power. (2) The MSEL[4:0] pins select the configuration scheme (AS, PS, JTAG, FPP); incorrect strapping resistors prevent boot. (3) Cyclone 10 GX requires a specific power-on sequence per the family datasheet - core voltage (0.9 V) must stabilize before I/O voltages. (4) Do not exceed the maximum I/O bank supply voltage (3.3 V LVCMOS or 1.8 V/1.5 V/1.2 V HSTL/SSTL). (5) Industrial-grade parts may require special ordering codes; verify 'I' suffix in the part number when sourcing from distributors.
Compliance Information
RoHS compliant per Intel product environmental documentation. Industrial temperature grade only; AEC-Q100 qualified variants available in other Cyclone 10 GX SKUs. Halogen-free status should be verified via Intel Product Compliance declaration.
