10AX115H4F34I3LG - Arria 10 GX 1.15M Logic Elements FPGA | Intel
MPN: 10AX115H4F34I3LG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8500 | $8,500.00 |
| 10 | $7800 | $78,000.00 |
| 100 | $6950 | $695,000.00 |
| 500 | $6100 | $3,050,000.00 |
| 1,000 | $5550 | $5,550,000.00 |
Drop-in alternatives for 10AX115H4F34I3LG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AX115H4F34I3SG
β Drop-Inπ Reference alternative (not in catalog)
10AX115H4F34I2LG
β Drop-Inπ Reference alternative (not in catalog)
10AX115H3F34I3LG
β Drop-Inπ Reference alternative (not in catalog)
10AX115H3F34I2LG
β Drop-Inβ In Stock
$6800 / Unit
View Datasheet β10AX115H3F34I2SG
β Drop-Inβ In Stock
$3675 / Unit
View Datasheet β10AX115H2F34I2LG
β Drop-Inβ In Stock
$4995 / Unit
View Datasheet β10AX115H2F34I2SG
β Drop-Inβ In Stock
$3640 / Unit
View Datasheet β10AX115H4F34I3LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LE) | 1,150,000 |
| Embedded Memory Bits | 68,857,600 |
| Maximum User I/O | 504 |
| Transceivers | 24 high-speed transceivers up to 17.4 Gbps |
| Hard Processor System | Optional (HPS) |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Speed Grade | -4 (fastest) |
| Transceiver Variant | H4 (high-performance) |
| Package | 1152-ball FCBGA (F34) |
| Operating Temperature | -40C to +100C (Industrial) |
| RoHS Status | Compliant |
| Configuration | Partial reconfiguration supported |
| External Memory Interfaces | DDR4 with ECC, up to 16.7 Gbps |
10AX115H4F34I3LG 1152-ball fcbga (f34) Pin Configuration Guide
Complete pinout information for 10AX115H4F34I3LG (1152-ball fcbga (f34) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX115H4F34I3LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115H4F34I3LG is suitable for 6 applications: 100G Optical Transport Line Cards, Wireless Baseband Processing (CPRI Fronthaul), High-Performance Computing Acceleration Cards, Broadcast Video Processing and Switching, Test and Measurement Equipment, Defense and Aerospace Signal Processing.
100G Optical Transport Line Cards
The 10AX115H4F34I3LG's 24 transceivers at 17.4 Gbps and 1.15M logic elements make it ideal for 100G OTN/Ethernet line cards requiring multiple 10G/25G channels plus a large OTN framer or MAC in fabric. Placed as the central processing device with QSFP28 optics on the line side, it delivers timing closure margin in the -4 grade that single-channel designs cannot match. The trade-off versus dedicated 100G ASSPs is flexibility to add proprietary features, at the cost of higher power and BOM.
Recommended
Wireless Baseband Processing (CPRI Fronthaul)
The 10AX115H4F34I3LG is well-suited to CPRI fronthaul baseband units that aggregate multiple 4G/5G radio carriers. With 24 transceivers at up to 17.4 Gbps, it can support 12 CPRI Option 7 links to remote radio heads while leaving sufficient fabric for PHY-layer DSP, scrambling, and IQ compression. The H4 high-performance variant provides the timing margin required for the most demanding LTE/5G NR symbol rates, while the industrial temperature grade supports outdoor cabinet deployments.
Recommended
High-Performance Computing Acceleration Cards
Deploy the 10AX115H4F34I3LG on PCIe Gen3 x8 accelerator cards for HPC, AI inference offload, or financial computing workloads. With 1.15M logic elements available, designers can implement hundreds of parallel compute engines with DDR4 memory-side bandwidth exceeding 16 Gbps. The H4 transceiver variant provides the Gen3 x8 hard IP plus headroom for additional Gen3 x4 or SATA channels. For pure inference workloads with lower compute density, the -3 grade variant (10AX115H3F34I3LG) may suffice at lower cost.
Recommended
Broadcast Video Processing and Switching
Use the 10AX115H4F34I3LG for broadcast video routers, format converters, and IP-to-SDI gateway designs that demand multi-channel processing. With 24 transceivers supporting SMPTE ST 2022 / ST 2110 video-over-IP plus 504 user I/O accommodating dozens of SDI streams, the device handles broadcast studio workloads where 12G-SDI and quad-link 3G-SDI are simultaneously present. The -4 speed grade ensures clean timing closure at the 148.5 MHz pixel clock typical of UHD video processing pipelines.
Recommended
Test and Measurement Equipment
Integrate the 10AX115H4F34I3LG in high-end oscilloscopes, protocol analyzers, and bit-error-rate testers that need simultaneous high-speed data acquisition and flexible pattern generation. The device's 24 transceivers enable parallel multi-lane protocol testing up to 17.4 Gbps per channel, while 1.15M logic elements provide real-time signal processing and protocol decoding. Industrial temperature grade supports production-line test environments, while the -4 speed grade handles the fastest signal-edge analysis scenarios.
Recommended
Defense and Aerospace Signal Processing
The 10AX115H4F34I3LG fits defense signal-intelligence and radar-processing applications where high-density logic combined with secure transceivers is required. With 24 transceivers supporting high-speed ADC/DAC interfacing plus 1.15M logic elements for real-time FFT, beamforming, and digital down-conversion, the device meets the throughput demands of electronic-warfare subsystems. The industrial temperature grade supports avionics bays, while partial reconfiguration enables runtime algorithm swaps in field-deployable systems.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115H4F34I3LG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115H4F34I3SG | 10AX115H4F34I2LG | 10AX115H3F34I3LG | 10AX115H3F34I2LG |
|---|---|---|---|---|---|
| Package | 1152-ball FCBGA (F34) | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same | 1152-ball FCBGA (F34) - same |
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 |
| Speed Grade | -4 (fastest) | -4 | -2 | -3 | -3 |
| Temperature Grade | Industrial (-40C to +100C) | Commercial | Industrial | Industrial | Industrial |
| Transceivers | 24 channels up to 17.4 Gbps | 24 channels up to 17.4 Gbps | 24 channels up to 17.4 Gbps | 24 channels up to 17.4 Gbps | 24 channels up to 17.4 Gbps |
| Maximum User I/O | 504 | 504 | 504 | 504 | 504 |
| Embedded Memory | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits | 68,857,600 bits |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
Key Differentiators
- Highest Fmax in the Arria 10 family with -4 speed grade (vs 10AX115H3F34I3LG (-3 grade))
- Industrial temperature grade for harsh environments (vs 10AX115H4F34I3SG (commercial grade))
- H4 high-performance transceiver variant (vs 10AX115N4F34I3LG (lower transceiver count variant))
Design Notes
Estimated: A 1152-ball FCBGA Arria 10 GX device at full utilization typically dissipates 15-25 W depending on transceiver activity and clock frequency. Designers must include a thermal via array beneath the package (typically 0.3 mm pitch, filled and capped) and a heat sink with adequate airflow to keep junction temperature below 100 C for industrial-grade parts. Without active cooling, sustained high utilization will exceed the industrial temperature rating.
The Arria 10 GX requires multiple independent supply rails: 0.9 V core (VCC), 0.9 V transceiver analog (VCCH_GXB), and per-bank I/O voltages (VCCIO at 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V). Power sequencing must follow the Arria 10 Power Management User Guide to avoid latch-up. Use a dedicated power controller such as the LTC2977 or equivalent Intel-recommended PMIC to manage ramp rates and fault response. Estimated total bulk capacitance requirement is 220-440 ΞΌF distributed across the supply rails.
Place the configuration flash within 6 inches of the FPGA to ensure reliable MSEL-based configuration at the supported modes (AS, PS, FPP, JTAG). Maintain impedance-controlled 100-ohm differential routing for all transceiver channels using the stackup recommended in the Arria 10 GX Transceiver User Guide. Provide sufficient decoupling: one 0.1 ΞΌF 0402 capacitor per power pin and bulk 22-47 ΞΌF per supply rail within 0.5 inch of the package.
Do not assume the speed grade alone determines Fmax; voltage, temperature, and the specific design structure (DSP-heavy vs memory-heavy vs routing-heavy) all affect achievable clock rates. Always run the Quartus Prime Slow 900 mV / 100 C model for industrial timing closure, and the Slow 1080 mV / -40 C model for low-temperature hold-time analysis. Leaving MSEL pins floating or misconfigured prevents configuration - use the Altera-recommended pull resistor configuration.
Compliance Information
RoHS and lead-free per Altera product page. Not AEC-Q100 qualified - automotive applications should consult Intel for AEC-Q100 variants or choose Cyclone V automotive parts.
