10CX085YF672I5G - 85K LE Cyclone 10 GX FPGA, 672-BGA | Intel
MPN: 10CX085YF672I5G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $33.38 | $33.38 |
| 10 | $30.21 | $302.10 |
| 100 | $26.84 | $2,684.00 |
| 250 | $24.12 | $6,030.00 |
| 500 | $22.05 | $11,025.00 |
| 1,000 | $19.78 | $19,780.00 |
Drop-in alternatives for 10CX085YF672I5G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10CX085YF672I6G
✅ Drop-In✓ In Stock
$255 / Unit
View Datasheet →10CX085YF672E6G
✅ Drop-In✓ In Stock
$280.5 / Unit
View Datasheet →10CX085YF672E5G
✅ Drop-In✓ In Stock
$289 / Unit
View Datasheet →10CX105YF672I5G
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$108 / Unit
View Datasheet →10CX105YF672I6G
✅ Drop-In✓ In Stock
$338 / Unit
View Datasheet →10CX150YF672I7G
✅ Drop-In📋 Reference alternative (not in catalog)
10CX085YF672I5G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 GX |
| Logic Elements (LE) | 85000 |
| Adaptive Logic Modules (ALM) | 31000 ALM |
| Embedded Memory | 5.68 Mbit (5,959,680 bits) |
| Embedded Multipliers (18x18) | 216 |
| User I/Os | 192 |
| Process Technology | 20 nm |
| Package | 672-BGA (F672, FineLine BGA) |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Operating Supply Voltage (Core) | 0.9 V |
| Mounting Type | Surface Mount |
| Maximum LVDS Speed | 1.5 Gbps (LVDS), up to 1.866 Gbps on selected banks |
| DSP Blocks | Hardened floating-point capable variable-precision DSP |
| PCI Express Hard IP | PCIe Gen2 x1/x2/x4 capable (per die, F672 pinout) |
| MSL Level | 3 (per BGA JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10CX085YF672I5G 672-bga (f672, fineline bga) Pin Configuration Guide
Complete pinout information for 10CX085YF672I5G (672-bga (f672, fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10CX085YF672I5G.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CX085YF672I5G is suitable for 6 applications: Industrial Machine Vision Cameras, Video Broadcast and Processing, PCI Express Endpoint Cards, Motor Control and Industrial Automation, Wired Communications Backplanes, Medical Imaging and Diagnostics.
Industrial Machine Vision Cameras
The 10CX085YF672I5G is well-matched to industrial machine vision, where 192 user I/Os accept multiple MIPI CSI-2, sub-LVDS, or parallel LVDS image sensors concurrently. Its 216 18x18 multipliers accelerate Bayer demosaicing and edge-detection kernels at line rates beyond 1080p60, while the 5.68 Mbit of embedded SRAM buffers full frames and lookup tables without external memory. The industrial -40 C to +85 C operating temperature supports factory-floor enclosures, and the 0.9 V core simplifies PoL regulator selection. Designers pair the FPGA with a single DDR3L memory for higher-resolution pipelines, leaving the on-chip M20K blocks for line buffers and coefficient storage.
Recommended
Video Broadcast and Processing
The 10CX085YF672I5G's hardened PCI Express Gen2 x4 and up to 1.5 Gbps LVDS I/O make it an efficient platform for broadcast video bridging. Engineers implement SDI-to-IP gateways, HDR tone mapping, and multi-stream scalers while keeping power below 10 W typical, which suits fanless rackmount chassis. The 216 DSP blocks deliver real-time 3D-LUT and color-space conversion at 4K60, and the on-chip transceivers (where available) free up external PHY chips. Quartus Prime IP for SMPTE ST 2059 / PTP precision-time-protocol and SDI embedding further reduces time-to-market.
Recommended
PCI Express Endpoint Cards
The 10CX085YF672I5G integrates PCIe Gen2 hard IP that supports endpoint configurations at x1, x2, or x4 lane widths, allowing cost-effective data-acquisition and protocol-bridge cards. A typical reference design places the FPGA behind a PCIe x4 edge connector, routing its 1.5 Gbps transceivers through AC-coupling caps to the host slot. The 85,000 LE and 216 multipliers handle DMA engine, scatter-gather descriptors, and on-board signal-processing simultaneously. Industrial temperature grade supports outdoor and ruggedized deployment for defense and test-equipment applications.
Recommended
Motor Control and Industrial Automation
The 10CX085YF672I5G delivers deterministic multi-axis motor control for industrial drives, with up to 192 I/Os that interface directly to encoder feedback, resolver-to-digital converters, and gate-driver interfaces. Its 216 multipliers accelerate Park/Clarke transforms and SVPWM modulation at loop rates up to 100 kHz per axis. The 5.68 Mbit embedded memory stores control-loop coefficients and fault logs, while the hardened PCIe Gen2 IP supports EtherCAT and PROFINET bridges. Industrial temperature and 20 nm low-static-power technology reduce thermal budget in sealed inverter cabinets.
Recommended
Wired Communications Backplanes
The 10CX085YF672I5G serves as a low-cost protocol-bridging FPGA in telecom and datacom backplanes, converting between 1G/10G Ethernet, Interlaken, and proprietary backplane SerDes rates. Its hardened transceivers reduce BOM cost relative to discrete PHY solutions, and the large I/O count supports parallel LVDS links to legacy line cards. Engineers implement hitless protection switching and pseudo-wire emulation entirely in user logic, while on-chip M20K blocks buffer cell/packet traffic at line rate. The same F672 pinout is shared with other Cyclone 10 GX densities, enabling smooth migrations as capacity grows.
Recommended
Medical Imaging and Diagnostics
The 10CX085YF672I5G is suitable for medical imaging modalities such as ultrasound front-end processing and endoscopy, where its 216 DSP blocks and 5.68 Mbit embedded memory accelerate beamforming and pixel correction at clinically required frame rates. The 192 user I/Os accept multiple AFE inputs (e.g., 16-channel ADC parallel buses) and provide LVDS outputs to back-end processors. Industrial temperature grade plus IEC 62471-compliant design practices support diagnostic-cart and bedside-monitor deployments. PCIe Gen2 hard IP enables low-latency image transfer to host CPUs.
Recommended
Recommended Products Summary
Engineering reference data for 10CX085YF672I5G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CX085YF672I6G | 10CX085YF672E6G | 10CX105YF672I5G | 10CX150YF672I7G |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 672-BGA (F672) | 672-BGA (F672) - same | 672-BGA (F672) - same | 672-BGA (F672) - same | 672-BGA (F672) - same |
| Logic Elements | 85000 | 85000 | 85000 | 105000 | 150000 |
| ALMs | 31000 ALM | 31000 ALM | 31000 ALM | 39000 ALM | 56000 ALM |
| Embedded Memory | 5.68 Mbit | 5.68 Mbit | 5.68 Mbit | 6.85 Mbit | 7.65 Mbit |
| Embedded Multipliers (18x18) | 216 | 216 | 216 | 288 | 336 |
| User I/Os | 192 | 192 | 192 | 192 | 192 |
| Speed Grade | I5 (industrial, speed grade 5) | I6 (industrial, speed grade 6) | E6 (commercial, speed grade 6) | I5 (industrial, speed grade 5) | I7 (industrial, speed grade 7) |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | 0 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
Key Differentiators
- Highest I/O count of the Cyclone 10 GX 10CX085 die (vs F484 / F256 packages of same die)
- Step-up density migration within same package (vs 10CX085YF672I6G same F672 package)
- Industrial temperature range with speed grade 5 (vs 10CX085YF672E6G same F672 commercial temp)
Design Notes
Route power-first for the 0.9 V core rail. Place 4 to 6 decoupling capacitors (1 x 470 uF bulk, 2 x 22 uF ceramic, and 4 to 6 x 0.1 uF 0201) within 5 mm of the F672 package BGA balls. The 27 mm x 27 mm FBGA land pattern requires a 12-layer or 14-layer stack-up with continuous ground planes directly beneath the package to provide return paths for high-speed LVDS and PCIe signals.
Estimated: at typical utilization (70% LE, 50% DSP, full transceiver traffic) the 10CX085 dissipates approximately 6 to 8 W, which requires a thermal management strategy. Use a thermal via array under the central BGA region connecting to an inner copper plane or external heatsink, sized to keep junction temperature below 100 C. Industrial variants (I5) require thermal validation across the full -40 C to +85 C range.
Do not assume all 192 I/Os support every I/O standard simultaneously. I/O bank voltage compatibility must be verified per pin using Pin Planner before schematic freeze. Also, transceiver reference-clock routing must be length-matched within 5 mil on the PCB; mismatched P/N traces will degrade eye margin at 10 Gbps. Finally, configure MSEL pins correctly for the desired configuration scheme (AS, PS, JTAG).
Differential pairs (LVDS, PCIe) require 100-ohm differential impedance. Use 8-mil-wide traces with 7-mil spacing on a stack-up targeting 85-ohm single-ended impedance. Series AC-coupling capacitors on PCIe transmit pairs must be placed symmetrically within 360 mil of the BGA via. Maintain reference-plane continuity beneath all high-speed traces; no ground-plane splits are allowed under BGA breakouts.
Compliance Information
RoHS and REACH compliant per Altera/Intel product page. BGA package MSL 3 rating. Not AEC-Q100 qualified - this part is not intended for automotive-grade deployments.
