5M160ZT100C5N - MAX V CPLD, 128 Macro Cells, TQFP-100 | Altera
MPN: 5M160ZT100C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.85 | $7.85 |
| 10 | $7.1 | $71.00 |
| 100 | $6.25 | $625.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.75 | $4,750.00 |
Drop-in alternatives for 5M160ZT100C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M160ZT100C4N
β Drop-Inβ In Stock
$4.95 / Unit
View Datasheet β5M160ZT100A5N
β Drop-Inβ In Stock
$4.9 / Unit
View Datasheet β5M160ZM100C5N
β Drop-Inβ In Stock
$4.35 / Unit
View Datasheet β5M240ZT100C5N
β Drop-Inβ In Stock
$4.9816 / Unit
View Datasheet β5M160ZT100C5N Maximum Ratings & Electrical Characteristics
| Series | MAX V |
| Device Family | MAX V CPLD |
| Macro Cells | 128 |
| Logic Elements (LEs) | 160 |
| User I/Os | 79 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD) | 7.5 ns |
| Maximum Operating Frequency | 152 MHz (typical, internal) |
| User Flash Memory (UFM) | 8 Kbits |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.5 V to 3.3 V |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) |
| Package | TQFP-100 |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Programming Interface | JTAG (IEEE 1149.1) - in-system |
5M160ZT100C5N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | GND β Ground |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | GND β Ground |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 4) |
| Pin 53 | I/O β User I/O pin (bank 4) |
| Pin 54 | GND β Ground |
| Pin 55 | I/O β User I/O pin (bank 4) |
| Pin 56 | I/O β User I/O pin (bank 4) |
| Pin 57 | I/O β User I/O pin (bank 4) |
| Pin 58 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 59 | I/O β User I/O pin (bank 4) |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 4) |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | GND β Ground |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 1) |
| Pin 72 | I/O β User I/O pin (bank 1) |
| Pin 73 | I/O β User I/O pin (bank 1) |
| Pin 74 | GND β Ground |
| Pin 75 | TMS β JTAG Test Mode Select |
| Pin 76 | TCK β JTAG Test Clock |
| Pin 77 | TDI β JTAG Test Data In |
| Pin 78 | TDO β JTAG Test Data Out |
| Pin 79 | VCCINT β Core supply voltage (1.8 V) |
| Pin 80 | I/O β User I/O pin (bank 1) |
| Pin 81 | I/O β User I/O pin (bank 1) |
| Pin 82 | I/O β User I/O pin (bank 1) |
| Pin 83 | I/O β User I/O pin (bank 1) |
| Pin 84 | I/O β User I/O pin (bank 1) |
| Pin 85 | I/O β User I/O pin (bank 1) |
| Pin 86 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 87 | I/O β User I/O pin (bank 1) |
| Pin 88 | I/O β User I/O pin (bank 1) |
| Pin 89 | I/O β User I/O pin (bank 1) |
| Pin 90 | I/O β User I/O pin (bank 1) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin (bank 1) |
| Pin 93 | I/O β User I/O pin (bank 1) |
| Pin 94 | I/O β User I/O pin (bank 1) |
| Pin 95 | I/O β User I/O pin (bank 1) |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 100 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZT100C5N is suitable for 6 applications: Microcontroller I/O Expansion, Bus Interface Bridging, Power Sequencing & Supervisor Logic, Address Decoding in Memory Subsystems, Industrial Control Logic Replacement, LED Display & Signage Driving.
Microcontroller I/O Expansion
The 5M160ZT100C5N expands MCU I/O count when 79 user pins are available in TQFP-100 to drive LEDs, keypads, and parallel peripherals beyond the MCU's native pin budget. Its 7.5 ns tPD and 1.5β3.3 V VCCIO support let it bridge directly to 1.8 V Cortex-M GPIO or 3.3 V legacy microcontrollers without level shifters, and the non-volatile instant-on boot means peripherals are ready before the MCU finishes its PLL lock. Quartus Prime pin planner assigns signals across the 8 LABs, and the 8 Kbit UFM can store board-level configuration that the MCU reads back at startup.
Recommended
Bus Interface Bridging
In legacy-to-modern board transitions, the 5M160ZT100C5N bridges 8-bit parallel buses to 16-bit or SPI peripherals without a costly FPGA. The 152 MHz internal frequency and 7.5 ns tPD comfortably meet 50 MHz parallel interfaces, while the 79 I/Os absorb address latches, chip selects, and data/control signals in a single chip. The MAX V flash stores the bridge personality so production boards can swap bus mappings via JTAG without firmware changes, and the industrial-grade variant handles β40 Β°C automotive under-hood retrofits.
Recommended
Power Sequencing & Supervisor Logic
The 5M160ZT100C5N replaces stacks of discrete 74-series logic in multi-rail power sequencing for FPGA, ASIC, and SoC boards. Its deterministic timing lets it assert enable signals in a fixed sequence (e.g., 1.0 V β 1.8 V β 3.3 V) with microsecond accuracy, and the 8 Kbit UFM stores trim values and fault counters that survive power cycling. Compared to a CPLD-based FPGA, the MAX V's 1.8 V core consumes less than 25 mW static, making it suitable for always-on supervisor rails.
Recommended
Address Decoding in Memory Subsystems
When interfacing external SRAM, NOR flash, or SDRAM to a processor with limited chip-select lines, the 5M160ZT100C5N decodes the upper address bits into individual /CS strobes. The 128 macro cells comfortably implement >20 chip selects with overlapping and ignore-window logic, and the 7.5 ns tPD adds minimal wait-state penalty at 50 MHz bus speeds. Because the decode map is flash-stored, late-stage PCB revisions can remap memory regions without respinning the processor board.
Recommended
Industrial Control Logic Replacement
A single 5M160ZT100C5N replaces dozens of 74HC/74AHC glue-logic ICs on industrial PLC backplanes, shrinking the BOM and easing long-term obsolescence management. The 79 I/Os handle sensor inputs, optocoupler outputs, and stepper/direction signals for motor-driver interfaces. Industrial temperature variants (5M160ZE64I5N in EQFP-64, 5M160ZT100I5N in TQFP-100) extend operation to β40 Β°C to +100 Β°C ambient typical of factory-floor cabinets.
Recommended
LED Display & Signage Driving
With 79 user I/Os and deterministic timing, the 5M160ZT100C5N drives multiplexed 7-segment, dot-matrix, or addressable-LED strings without an MCU intervention. The 8 Kbit UFM stores frame patterns and animations, allowing the host to upload a sequence and let the CPLD refresh the LEDs autonomously β freeing the MCU for higher-level tasks. Quartus Prime State Machine templates implement Charlieplex and matrix scanning in under 30 macro cells, leaving headroom for brightness PWM control.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZT100C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZT100C4N | 5M160ZT100A5N | 5M160ZM100C5N | 5M240ZT100C5N |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Logic Elements | 160 LEs | 160 LEs | 160 LEs | 160 LEs | 240 LEs (+50%) |
| Macro Cells | 128 | 128 | 128 | 128 | 192 (+50%) |
| Speed Grade (tPD) | 7.5 ns (C5) | 4.5 ns (C4, faster) | 10 ns (A5, slower) | 7.5 ns (C5) | 7.5 ns (C5) |
| User I/Os | 79 | 79 | 79 | 79 | 79 |
| UFM Size | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit | 8 Kbit |
| Operating Temperature | 0 Β°C to +85 Β°C | 0 Β°C to +85 Β°C | 0 Β°C to +85 Β°C | 0 Β°C to +85 Β°C | 0 Β°C to +85 Β°C |
| Drop-in for 5M160ZT100C5N | β | Yes (same die, faster speed) | Yes (same die, slower speed) | Yes (same die, M-bank variant) | Yes (larger die, same footprint) |
Key Differentiators
- Largest logic capacity in the 5M160 TQFP-100 family (vs 5M160ZT100C4N)
- Faster speed grade within the same die (vs 5M160ZT100A5N)
- I/O bank variant with M-grade ESD protection (vs 5M160ZM100C5N)
Design Notes
Decoupling: place a 0.1 Β΅F X7R 0402/0603 capacitor within 3 mm of every VCCINT and VCCIO pin, plus a single 10 Β΅F bulk tantalum or ceramic near the package. The 5M160ZT100C5N draws transient current spikes of 100β200 mA during simultaneous logic switching across 8 LABs, so per-pin decoupling is mandatory to maintain VCCIO tolerance. Route GND returns directly to a continuous ground plane under the device β avoid daisy-chained GND traces which inject switching noise into the 1.8 V core.
JTAG chain integrity: keep the four JTAG pins (TCK, TMS, TDI, TDO) short and matched within 25 mm on the PCB to avoid marginal sampling during in-system programming. Place a 10 kΞ© pull-up on TMS and TDI per IEEE 1149.1 recommendations to hold the bus in a benign state at power-up before the CPLD configures its JTAG engine. If using a shared JTAG chain with other devices, include a series 33 Ξ© resistor on TDO outputs to dampen reflections.
Bank voltage mixing: the 5M160ZT100C5N has four I/O banks; mixing 1.5 V and 3.3 V on the same bank causes contention and possible latch-up. Quartus Prime's pin planner will flag this as an error, but manual pin assignments in legacy designs can bypass the check. Always re-validate the pin-out with the 'I/O Bank Analysis' tool after any hand-edits. Additionally, the dedicated VCCINT (1.8 V) pin must NEVER be tied to a 3.3 V rail β doing so destroys the flash cells within seconds.
Compliance Information
Lead-free, RoHS-compliant per Altera/Intel product declaration. Commercial temperature grade only (0 Β°C to +85 Β°C); not AEC-Q100 qualified β choose the I-suffix variant for automotive/industrial.
