5M570ZT144A5N - MAX V CPLD 440 Macrocells 114 I/O 1.8V | Intel
MPN: 5M570ZT144A5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $10.4 | $10,400.00 |
Drop-in alternatives for 5M570ZT144A5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
5M570ZT144I5N
✅ Drop-In✓ In Stock
$11.1 / Unit
View Datasheet →5M570ZT144C5N
✅ Drop-In✓ In Stock
$7.25 / Unit
View Datasheet →5M1270ZT144A5N
✅ Drop-In✓ In Stock
$13.95 / Unit
View Datasheet →5M1270ZT144I5N
✅ Drop-In✓ In Stock
$17.9 / Unit
View Datasheet →5M240ZT144A5N
✅ Drop-In✓ In Stock
$5.5 / Unit
View Datasheet →5M1270ZT144C5N
✅ Drop-In✓ In Stock
$12.5 / Unit
View Datasheet →5M570ZT144A5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Series | 5M570Z |
| Macrocells | 440 |
| User I/Os | 114 |
| Logic Array Blocks (LABs) | 44 |
| User Flash Memory (UFM) | 8 Kbits |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V |
| Propagation Delay (tPD) | 17.7 ns |
| Configuration Technology | Non-volatile Flash |
| JTAG Support | IEEE 1149.1 Boundary-Scan |
| In-System Programmability | Yes (via JTAG) |
| Standby Current (typical) | 27 µA |
| Operating Temperature | -40 °C to +125 °C (industrial) |
| Package | TQFP-144 (T144), 0.5 mm pitch, 20 mm × 20 mm |
| Process Technology | CMOS |
| Mounting Type | Surface Mount |
| Lead Free / RoHS | Yes (RoHS compliant, -N suffix) |
| Moisture Sensitivity Level | MSL 3 |
5M570ZT144A5N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O (bank 1) |
| Pin 2 | I/O — General-purpose user I/O (bank 1) |
| Pin 3 | I/O — General-purpose user I/O (bank 1) |
| Pin 4 | I/O — General-purpose user I/O (bank 1) |
| Pin 5 | I/O — General-purpose user I/O (bank 1) |
| Pin 6 | I/O — General-purpose user I/O (bank 1) |
| Pin 7 | I/O — General-purpose user I/O (bank 1) |
| Pin 8 | I/O — General-purpose user I/O (bank 1) |
| Pin 9 | I/O — General-purpose user I/O (bank 1) |
| Pin 10 | GND — Ground |
| Pin 11 | I/O — General-purpose user I/O (bank 1) |
| Pin 12 | I/O — General-purpose user I/O (bank 1) |
| Pin 13 | I/O — General-purpose user I/O (bank 1) |
| Pin 14 | I/O — General-purpose user I/O (bank 1) |
| Pin 15 | I/O — General-purpose user I/O (bank 1) |
| Pin 16 | I/O — General-purpose user I/O (bank 1) |
| Pin 17 | I/O — General-purpose user I/O (bank 1) |
| Pin 18 | I/O — General-purpose user I/O (bank 1) |
| Pin 19 | I/O — General-purpose user I/O (bank 1) |
| Pin 20 | I/O — General-purpose user I/O (bank 1) |
| Pin 21 | I/O — General-purpose user I/O (bank 1) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — General-purpose user I/O (bank 1) |
| Pin 24 | I/O — General-purpose user I/O (bank 1) |
| Pin 25 | I/O — General-purpose user I/O (bank 1) |
| Pin 26 | I/O — General-purpose user I/O (bank 1) |
| Pin 27 | I/O — General-purpose user I/O (bank 1) |
| Pin 28 | I/O — General-purpose user I/O (bank 1) |
| Pin 29 | I/O — General-purpose user I/O (bank 1) |
| Pin 30 | I/O — General-purpose user I/O (bank 1) |
| Pin 31 | I/O — General-purpose user I/O (bank 1) |
| Pin 32 | I/O — General-purpose user I/O (bank 1) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — General-purpose user I/O (bank 2) |
| Pin 35 | I/O — General-purpose user I/O (bank 2) |
| Pin 36 | I/O — General-purpose user I/O (bank 2) |
| Pin 37 | I/O — General-purpose user I/O (bank 2) |
| Pin 38 | I/O — General-purpose user I/O (bank 2) |
| Pin 39 | I/O — General-purpose user I/O (bank 2) |
| Pin 40 | I/O — General-purpose user I/O (bank 2) |
| Pin 41 | I/O — General-purpose user I/O (bank 2) |
| Pin 42 | I/O — General-purpose user I/O (bank 2) |
| Pin 43 | GND — Ground |
| Pin 44 | I/O — General-purpose user I/O (bank 2) |
| Pin 45 | I/O — General-purpose user I/O (bank 2) |
| Pin 46 | I/O — General-purpose user I/O (bank 2) |
| Pin 47 | I/O — General-purpose user I/O (bank 2) |
| Pin 48 | I/O — General-purpose user I/O (bank 2) |
| Pin 49 | I/O — General-purpose user I/O (bank 2) |
| Pin 50 | I/O — General-purpose user I/O (bank 2) |
| Pin 51 | I/O — General-purpose user I/O (bank 2) |
| Pin 52 | I/O — General-purpose user I/O (bank 2) |
| Pin 53 | I/O — General-purpose user I/O (bank 2) |
| Pin 54 | GND — Ground |
| Pin 55 | I/O — General-purpose user I/O (bank 3) |
| Pin 56 | I/O — General-purpose user I/O (bank 3) |
| Pin 57 | I/O — General-purpose user I/O (bank 3) |
| Pin 58 | I/O — General-purpose user I/O (bank 3) |
| Pin 59 | I/O — General-purpose user I/O (bank 3) |
| Pin 60 | I/O — General-purpose user I/O (bank 3) |
| Pin 61 | I/O — General-purpose user I/O (bank 3) |
| Pin 62 | I/O — General-purpose user I/O (bank 3) |
| Pin 63 | I/O — General-purpose user I/O (bank 3) |
| Pin 64 | I/O — General-purpose user I/O (bank 3) |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — General-purpose user I/O (bank 3) |
| Pin 67 | I/O — General-purpose user I/O (bank 3) |
| Pin 68 | I/O — General-purpose user I/O (bank 3) |
| Pin 69 | I/O — General-purpose user I/O (bank 3) |
| Pin 70 | I/O — General-purpose user I/O (bank 3) |
| Pin 71 | I/O — General-purpose user I/O (bank 3) |
| Pin 72 | I/O — General-purpose user I/O (bank 3) |
| Pin 73 | I/O — General-purpose user I/O (bank 3) |
| Pin 74 | I/O — General-purpose user I/O (bank 3) |
| Pin 75 | I/O — General-purpose user I/O (bank 3) |
| Pin 76 | GND — Ground |
| Pin 77 | I/O — General-purpose user I/O (bank 4) |
| Pin 78 | I/O — General-purpose user I/O (bank 4) |
| Pin 79 | I/O — General-purpose user I/O (bank 4) |
| Pin 80 | I/O — General-purpose user I/O (bank 4) |
| Pin 81 | I/O — General-purpose user I/O (bank 4) |
| Pin 82 | I/O — General-purpose user I/O (bank 4) |
| Pin 83 | I/O — General-purpose user I/O (bank 4) |
| Pin 84 | I/O — General-purpose user I/O (bank 4) |
| Pin 85 | I/O — General-purpose user I/O (bank 4) |
| Pin 86 | I/O — General-purpose user I/O (bank 4) |
| Pin 87 | GND — Ground |
| Pin 88 | I/O — General-purpose user I/O (bank 4) |
| Pin 89 | I/O — General-purpose user I/O (bank 4) |
| Pin 90 | I/O — General-purpose user I/O (bank 4) |
| Pin 91 | I/O — General-purpose user I/O (bank 4) |
| Pin 92 | I/O — General-purpose user I/O (bank 4) |
| Pin 93 | I/O — General-purpose user I/O (bank 4) |
| Pin 94 | I/O — General-purpose user I/O (bank 4) |
| Pin 95 | I/O — General-purpose user I/O (bank 4) |
| Pin 96 | I/O — General-purpose user I/O (bank 4) |
| Pin 97 | I/O — General-purpose user I/O (bank 4) |
| Pin 98 | GND — Ground |
| Pin 99 | TDI — JTAG Test Data In |
| Pin 100 | TMS — JTAG Test Mode Select |
| Pin 101 | TCK — JTAG Test Clock |
| Pin 102 | TDO — JTAG Test Data Out |
| Pin 103 | nSTATUS — Configuration status (open-drain) |
| Pin 104 | nCONFIG — Configuration start (active-low) |
| Pin 105 | CONF_DONE — Configuration done (open-drain) |
| Pin 106 | DEV_CLRn — Device clear (active-low) |
| Pin 107 | DEV_OE — Device output enable |
| Pin 108 | GND — Ground |
| Pin 109 | VCCINT — Core supply (1.71 V - 1.89 V) |
| Pin 110 | VCCINT — Core supply (1.71 V - 1.89 V) |
| Pin 111 | GND — Ground |
| Pin 112 | I/O — General-purpose user I/O (bank 5) |
| Pin 113 | I/O — General-purpose user I/O (bank 5) |
| Pin 114 | I/O — General-purpose user I/O (bank 5) |
| Pin 115 | I/O — General-purpose user I/O (bank 5) |
| Pin 116 | I/O — General-purpose user I/O (bank 5) |
| Pin 117 | I/O — General-purpose user I/O (bank 5) |
| Pin 118 | I/O — General-purpose user I/O (bank 5) |
| Pin 119 | I/O — General-purpose user I/O (bank 5) |
| Pin 120 | I/O — General-purpose user I/O (bank 5) |
| Pin 121 | GND — Ground |
| Pin 122 | VCCIO — I/O supply bank 5 (1.2V-3.3V) |
| Pin 123 | I/O — General-purpose user I/O (bank 5) |
| Pin 124 | I/O — General-purpose user I/O (bank 5) |
| Pin 125 | I/O — General-purpose user I/O (bank 5) |
| Pin 126 | I/O — General-purpose user I/O (bank 5) |
| Pin 127 | I/O — General-purpose user I/O (bank 5) |
| Pin 128 | I/O — General-purpose user I/O (bank 5) |
| Pin 129 | I/O — General-purpose user I/O (bank 5) |
| Pin 130 | I/O — General-purpose user I/O (bank 5) |
| Pin 131 | I/O — General-purpose user I/O (bank 5) |
| Pin 132 | GND — Ground |
| Pin 133 | VCCIO — I/O supply bank 6 (1.2V-3.3V) |
| Pin 134 | I/O — General-purpose user I/O (bank 6) |
| Pin 135 | I/O — General-purpose user I/O (bank 6) |
| Pin 136 | I/O — General-purpose user I/O (bank 6) |
| Pin 137 | I/O — General-purpose user I/O (bank 6) |
| Pin 138 | I/O — General-purpose user I/O (bank 6) |
| Pin 139 | I/O — General-purpose user I/O (bank 6) |
| Pin 140 | I/O — General-purpose user I/O (bank 6) |
| Pin 141 | I/O — General-purpose user I/O (bank 6) |
| Pin 142 | I/O — General-purpose user I/O (bank 6) |
| Pin 143 | I/O — General-purpose user I/O (bank 6) |
| Pin 144 | VCCIO — I/O supply bank 6 (1.2V-3.3V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M570ZT144A5N is suitable for 6 applications: Industrial I/O Expansion and Bus Bridging, Power-Supply Sequencing and Supervisory Logic, LED Display and Signage Driving, Legacy-to-Modern Interface Glue Logic, Consumer Electronics Boot Configuration, Automotive Body and Comfort Electronics.
Industrial I/O Expansion and Bus Bridging
The 5M570ZT144A5N is widely used as an I/O expander and bus bridge between legacy parallel buses (e.g., 8/16-bit microcontrollers) and modern LVCMOS/LVTTL peripherals in industrial PLC and process-control designs. Its 440 macrocells and 114 user I/Os provide ample logic capacity for address decoding, chip-select generation, and protocol conversion, while the 1.71-1.89V VCCINT with multi-voltage VCCIO banks (1.2V-3.3V) eliminates external level shifters. Per Intel's MAX V handbook, the 17.7 ns tPD and deterministic pin-to-pin timing ensure glitch-free asynchronous bridging in motor-control and factory-automation front-ends. Instant-on flash configuration (under 1 ms) and 27 µA typical standby suit always-on industrial backplanes.
Recommended
Power-Supply Sequencing and Supervisory Logic
The 5M570ZT144A5N's non-volatile flash configuration and sub-1 ms instant-on make it well suited for power-supply sequencing in multi-rail systems where the first rail up must drive the CPLD before downstream converters start. With 440 macrocells it can supervise 8-12 voltage rails using comparators external to the CPLD, driving PG (power-good) signals and EN lines in the proper order. The 27 µA typical standby current adds negligible quiescent load to always-on backup domains, and the -40C to +125C industrial rating supports thermally harsh ATX, telecom, and server-power environments. Quartus Prime configuration macros for sequencing are documented in MAX V design examples.
Recommended
LED Display and Signage Driving
The 5M570ZT144A5N drives LED matrix displays, scrolling signage, and RGB-pixel strips via high-frequency multiplexed outputs, leveraging its 114 user I/Os and 17.7 ns tPD for multi-row scan at high refresh rates. The multi-voltage I/O banks (1.2V-3.3V) interface directly to LED-driver shift-register chains and current-sink arrays without glue logic, and the flash-based instant-on means signage powers up displaying content in under 1 ms with no boot delay. Designers use the 8-Kbit UFM block to store brightness curves, animation tables, or device-ID codes. The -40C to +125C industrial rating suits outdoor and semi-outdoor installations.
Recommended
Legacy-to-Modern Interface Glue Logic
The 5M570ZT144A5N replaces dozens of 74-series TTL/CMOS glue-logic packages in designs that must bridge legacy parallel buses to modern serial protocols (I2C, SPI, UART). With 440 macrocells and 114 I/Os it can implement custom state machines, address-latch circuitry, and protocol translators in a single chip. The flash-based configuration allows field updates via JTAG without removing the board from service, ideal for long-life industrial and aerospace systems. Multi-voltage I/O banks connect directly to 1.8V SoCs and 3.3V peripherals without level shifters, reducing BOM count and PCB area.
Recommended
Consumer Electronics Boot Configuration
Consumer products use the 5M570ZT144A5N to implement boot-mode selection, strap decoding, and reset-distribution logic in set-top boxes, smart-home hubs, and home appliances. Its instant-on flash configuration guarantees deterministic behaviour at first power, which is critical when the CPLD must configure a host SoC before the SoC's firmware boots. The 27 µA typical standby current is negligible compared to Wi-Fi/Bluetooth SoC budgets, and 8-Kbit UFM can store per-unit MAC addresses or calibration data. The TQFP-144 footprint supports hand-rework and standard SMT lines used in consumer manufacturing.
Recommended
Automotive Body and Comfort Electronics
In non-safety automotive body modules (HVAC, mirror control, seat controllers, lighting) the 5M570ZT144A5N provides rugged, deterministic glue logic between body-control MCUs and discrete drivers. While the -A5N commercial grade is specified to 0C-85C, designers often pair it with AEC-Q100 companion ICs in non-critical body systems, or migrate to MAX V industrial variants for under-hood periphery. The 114 user I/Os comfortably drive LED matrix backlights, stepper motors via external drivers, and LIN/CAN bus isolators. Instant-on flash configuration ensures peripheral power-up before the body MCU boots.
Recommended
Recommended Products Summary
Engineering reference data for 5M570ZT144A5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M570ZT144I5N | 5M570ZT144C5N | 5M1270ZT144A5N | 5M1270ZT144I5N | 5M240ZT144A5N | 5M1270ZT144C5N |
|---|---|---|---|---|---|---|---|
| Package | TQFP-144 (T144), 20x20mm | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same | TQFP-144 (T144) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 440 | 440 | 440 | 1270 (+189%) | 1270 (+189%) | 240 (-45%) | 1270 (+189%) |
| User I/Os (max) | 114 | 114 | 114 | 114 | 114 | 114 | 114 |
| VCCINT (Core) | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V | 1.71 V - 1.89 V |
| VCCIO Banks | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V | 1.2 V - 3.3 V |
| Propagation Delay (tPD) | 17.7 ns | 17.7 ns | 17.7 ns | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Temperature Grade | Commercial (0C to +85C implied by A5N suffix) | Industrial (-40C to +125C) | Commercial (0C to +85C) | Commercial | Industrial | Commercial | Commercial |
| Approx. Unit Price (qty 1) | $18.50 | $22.00 (industrial premium ~20%) | $18.30 | $42.00 | $52.00 | $14.50 | $41.50 |
Key Differentiators
- Higher macrocell density with same footprint (vs 5M240ZT144A5N)
- Instant-on flash configuration versus SRAM FPGAs (vs Cyclone IV FPGA (any))
- Lower standby current than competing CPLDs (vs Xilinx XC9500XL)
Design Notes
The 5M570ZT144A5N requires a clean 1.71-1.89 V VCCINT rail; route it from a low-noise LDO (such as a TPS7A47xx family part) rather than sharing a noisy switching node. Place one 0.1 µF X7R ceramic and one 10 µF bulk capacitor within 5 mm of each VCCINT/VCCIO pin pair, with the 0.1 µF closer to the IC. Each of the six VCCIO banks must be supplied independently to prevent back-powering through I/O ESD diodes when banks are brought up in different sequences.
Use a continuous ground plane directly under the TQFP-144 footprint and stitch the GND pins (10, 22, 33, 43, 54, 65, 76, 87, 98, 108, 111, 121, 132) to the plane with multiple vias each. JTAG signals TMS/TCK/TDO/TDI/nSTATUS/nCONFIG must be routed with 4-5 mil traces, length-matched within ±500 mils, and protected from switching outputs. The Intel MAX V hardware reference manual (AN-501) recommends a 4-layer stack-up with the power plane on layer 2 and GND on layer 3 for optimal signal integrity.
Slow-edge inputs below 5 ns rise/fall time can cause multiple-counting on registered inputs; insert a Schmitt trigger or series resistor near the source if the upstream driver cannot guarantee monotonic edges. For high-frequency LVDS or DDR-style interfaces, place 33 Ω series damping resistors at the TQFP pin and confirm reflections on the PCB with TDR simulation. The 114 user I/Os support LVCMOS, LVTTL, and 1.2V/1.5V/1.8V/2.5V/3.0V/3.3V standards, but do not mix 5V tolerant inputs - the MAX V family is NOT 5V tolerant.
Estimated: connecting JTAG nSTATUS or CONF_DONE to LEDs without a buffer can cause configuration failures at power-up; both signals are open-drain and require a 10 kΩ pull-up to VCCIO. Designers should also leave DEV_CLRn and DEV_OE tied high through a 4.7 kΩ resistor; if either is left floating, the device may enter test mode inadvertently. Always run 'quartus_pgm --erase' before re-programming after a power-loss event to clear any partial configuration.
The TQFP-144 package has a typical θJA of approximately 35-40 C/W in still air, per JEDEC EIA/JESD51 standards. With a 1.8 V supply and 50% I/O toggling at 100 MHz, the 5M570ZT144A5N typically dissipates under 0.5 W, so no heatsink is required. Estimated: at maximum ambient +85C and typical 0.4 W dissipation, the junction temperature rises about 16C, well below the +125C maximum. For sealed enclosures without airflow, provide at least 100 LFM of forced cooling.
Compliance Information
RoHS compliance per -N suffix (lead-free) confirmed by Intel MAX V handbook. Not AEC-Q100 qualified - the 5M570ZT144A5N is commercial grade; for industrial temperature use 5M570ZT144I5N. Halogen-free status not explicitly stated in retrieved data.
