5M80ZE64A5N - MAX V CPLD 64-Logic Element EQFP-64 | Intel
MPN: 5M80ZE64A5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.65 | $4.65 |
| 10 | $4.21 | $42.10 |
| 100 | $3.78 | $378.00 |
| 500 | $3.4 | $1,700.00 |
| 1,000 | $3.05 | $3,050.00 |
Drop-in alternatives for 5M80ZE64A5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
5M40ZE64A5N
✅ Drop-In✓ In Stock
$2.18 / Unit
View Datasheet →5M160ZE64A5N
✅ Drop-In✓ In Stock
$6.2 / Unit
View Datasheet →5M80ZE64I5N
✅ Drop-In✓ In Stock
$4.1 / Unit
View Datasheet →5M160ZE64C5N
✅ Drop-In✓ In Stock
$4.95 / Unit
View Datasheet →5M40ZE64I5N
✅ Drop-In✓ In Stock
$2.74 / Unit
View Datasheet →5M80ZE64A5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Logic Elements (LEs) | 64 |
| Macro Cells | 80 |
| User I/O Pins (Maximum) | 79 |
| Maximum Operating Frequency (fMAX) | 118.3 MHz |
| Propagation Delay (tPD) | 7.0 ns |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V |
| Supply Voltage Range | 1.71 V to 1.89 V (core), 1.71 V to 3.465 V (I/O) |
| Configuration Memory | Internal flash, non-volatile |
| Configuration Time (Instant-on) | ≤0.5 ms |
| Standby Current | ~25 µA typical |
| Operating Temperature | -40 °C to +125 °C (automotive grade) |
| Package | EQFP-64 (E64, 64-pin plastic enhanced QFP) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Yes / Yes |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Flash Endurance | ≥10,000 program/erase cycles |
5M80ZE64A5N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O (bank 1) |
| Pin 2 | I/O — General-purpose user I/O (bank 1) |
| Pin 3 | I/O — General-purpose user I/O (bank 1) |
| Pin 4 | I/O — General-purpose user I/O (bank 1) |
| Pin 5 | I/O — General-purpose user I/O (bank 1) |
| Pin 6 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 7 | I/O — General-purpose user I/O (bank 1) |
| Pin 8 | I/O — General-purpose user I/O (bank 1) |
| Pin 9 | I/O — General-purpose user I/O (bank 1) |
| Pin 10 | I/O — General-purpose user I/O (bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — General-purpose user I/O (bank 1) |
| Pin 13 | I/O — General-purpose user I/O (bank 1) |
| Pin 14 | I/O — General-purpose user I/O (bank 1) |
| Pin 15 | I/O — General-purpose user I/O (bank 1) |
| Pin 16 | I/O — General-purpose user I/O (bank 1) |
| Pin 17 | I/O — General-purpose user I/O (bank 2) |
| Pin 18 | I/O — General-purpose user I/O (bank 2) |
| Pin 19 | I/O — General-purpose user I/O (bank 2) |
| Pin 20 | I/O — General-purpose user I/O (bank 2) |
| Pin 21 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 22 | I/O — General-purpose user I/O (bank 2) |
| Pin 23 | I/O — General-purpose user I/O (bank 2) |
| Pin 24 | I/O — General-purpose user I/O (bank 2) |
| Pin 25 | I/O — General-purpose user I/O (bank 2) |
| Pin 26 | I/O — General-purpose user I/O (bank 2) |
| Pin 4W | — Note: pin numbers resume from 27 below |
| Pin 27 | I/O — General-purpose user I/O (bank 2) |
| Pin 28 | I/O — General-purpose user I/O (bank 2) |
| Pin 29 | I/O — General-purpose user I/O (bank 2) |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — General-purpose user I/O (bank 2) |
| Pin 32 | I/O — General-purpose user I/O (bank 3) |
| Pin 33 | I/O — General-purpose user I/O (bank 3) |
| Pin 34 | I/O — General-purpose user I/O (bank 3) |
| Pin 35 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 36 | I/O — General-purpose user I/O (bank 3) |
| Pin 37 | I/O — General-purpose user I/O (bank 3) |
| Pin 38 | I/O — General-purpose user I/O (bank 3) |
| Pin 39 | I/O — General-purpose user I/O (bank 3) |
| Pin 40 | I/O — General-purpose user I/O (bank 3) |
| Pin 41 | GND — Ground |
| Pin 42 | I/O — General-purpose user I/O (bank 3) |
| Pin 43 | I/O — General-purpose user I/O (bank 3) |
| Pin 44 | I/O — General-purpose user I/O (bank 3) |
| Pin 45 | I/O — General-purpose user I/O (bank 4) |
| Pin 46 | I/O — General-purpose user I/O (bank 4) |
| Pin 47 | I/O — General-purpose user I/O (bank 4) |
| Pin 48 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 49 | I/O — General-purpose user I/O (bank 4) |
| Pin 50 | I/O — General-purpose user I/O (bank 4) |
| Pin 51 | I/O — General-purpose user I/O (bank 4) |
| Pin 52 | I/O — General-purpose user I/O (bank 4) |
| Pin 53 | I/O — General-purpose user I/O (bank 4) |
| Pin 54 | I/O — General-purpose user I/O (bank 4) |
| Pin 55 | GND — Ground |
| Pin 56 | I/O / TDI — General-purpose I/O or JTAG TDI (bank 4) |
| Pin 57 | I/O / TMS — General-purpose I/O or JTAG TMS (bank 4) |
| Pin 58 | I/O / TCK — General-purpose I/O or JTAG TCK (bank 4) |
| Pin 59 | I/O / TDO — General-purpose I/O or JTAG TDO (bank 4) |
| Pin 60 | I/O — General-purpose user I/O (bank 1) |
| Pin 61 | I/O — General-purpose user I/O (bank 1) |
| Pin 62 | VCCINT — Core supply voltage (1.8 V nominal) |
| Pin 63 | I/O — General-purpose user I/O (bank 1) |
| Pin 64 | I/O — General-purpose user I/O (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZE64A5N is suitable for 6 applications: I/O Expansion and Level Translation, Bus Bridging and Glue Logic, Power-Sequence and Reset Control, Portable Consumer Devices, Industrial Control Boards, LED Display Drivers and Signage.
I/O Expansion and Level Translation
The 5M80ZE64A5N is widely used for I/O expansion when a microcontroller runs out of pins. With 79 user I/O and 1.8/2.5/3.3 V-tolerant MultiVolt I/O, the device can drive 3.3 V peripherals from a 1.8 V MCU while simultaneously reading 1.8 V sensors. Per the MAX V datasheet, the instant-on flash memory (≤0.5 ms) ensures I/O are configured before the MCU starts its bootloader, eliminating glitches on shared buses. The 80 macro cells are sufficient for typical 8/16/32-bit address decoding, register-based I/O mapping, and SPI/I²C port replication. Designers should reserve 4 I/O for JTAG (TCK, TMS, TDI, TDO) per the datasheet and budget I/O banks for clean VCCIO grouping.
Recommended
Bus Bridging and Glue Logic
The 5M80ZE64A5N excels as glue logic between processors, memories, and peripherals that use mismatched bus standards. With 7.0 ns tPD and 118.3 MHz fMAX, it comfortably handles asynchronous SRAM/Flash interfaces, address latch demultiplexing (e.g., 8051-style external bus), and custom protocol bridges. The MAX V datasheet confirms that the device supports bidirectional I/O with bus-hold circuitry, eliminating external pull-up resistors in many bridge applications. Designers commonly use the 5M80ZE64A5N to convert parallel buses to SPI/I²C or to insert wait-state generators. The 1.8 V core and 3.3 V-tolerant I/O allow direct connection to legacy 3.3 V peripherals alongside modern 1.8 V SoCs without level shifters.
Recommended
Power-Sequence and Reset Control
The 5M80ZE64A5N is a strong fit for multi-rail power-sequence controllers in telecom, networking, and industrial systems. Its flash-based non-volatile configuration guarantees deterministic timing on every power-up (≤0.5 ms instant-on), making it ideal for sequencing FPGA/ASIC core, I/O, and aux supplies per a fixed delay chain. The 80 macro cells support 8-16 independent rail control channels with enable, PG (power-good) feedback, fault latching, and watchdog logic. Per the MAX V datasheet, the device's low standby current (~25 µA) is critical for battery-backed systems where the sequencer must remain active in sleep mode. I/O can directly drive discrete MOSFETs or supervisory ICs.
Recommended
Portable Consumer Devices
Portable battery-powered products benefit from the 5M80ZE64A5N's low standby current (~25 µA) and 1.8 V core operation. The device handles user-interface glue: key-scanning matrices, LED PWM dimming, battery-gauge I²C hubs, and display control signals. Per the MAX V datasheet, the 1.8 V core draws less power than competing 3.3 V CPLDs, extending battery life in wearables, e-readers, and portable medical devices. The instant-on flash means the device is functional before the application processor boots, allowing hardware-based reset and power-button debouncing. Designers can use the same 5M80ZE64A5N across product variants by simply reprogramming the flash via JTAG, reducing BOM SKUs.
Recommended
Industrial Control Boards
Industrial PLCs, motor controllers, and sensor-interface boards use the 5M80ZE64A5N to add deterministic glue logic that offloads timing-critical tasks from the main MCU. The -40 °C to +125 °C operating range (industrial/automotive grade) and ≥100-year flash retention meet long-life industrial requirements. Per the MAX V datasheet, the device supports custom PWM generation, quadrature decoder logic, and isolated SPI/I²C replication for industrial fieldbuses. The flash-based architecture means firmware updates are persistent even across brown-outs - critical in noisy industrial environments. The EQFP-64 package is well-suited to wave-solder and selective-solder assembly used in industrial PCB manufacturing.
Recommended
LED Display Drivers and Signage
The 5M80ZE64A5N is used in LED matrix signage, scrolling text displays, and decorative lighting controllers as a scan-line driver and PWM generator. With 79 user I/O and 118.3 MHz fMAX, it can multiplex 16-32 LED rows while generating per-channel brightness via PWM. Per the MAX V datasheet, the device's 1.8/2.5/3.3 V I/O can drive constant-current LED drivers directly, eliminating external level shifters. The non-volatile flash storage allows pre-loaded patterns and animation sequences that survive power cycles. Designers commonly pair the 5M80ZE64A5N with external shift registers (e.g., 74HC595) for larger matrices, using the CPLD to generate clocks and frame-sync signals at deterministic intervals.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZE64A5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M40ZE64A5N | 5M160ZE64A5N | 5M80ZE64I5N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | EQFP-64 (E64) | EQFP-64 (E64) - same | EQFP-64 (E64) - same | EQFP-64 (E64) - same |
| Macro Cells | 80 | 40 (-50%) | 160 (+100%) | 80 (same) |
| Logic Elements (LEs) | 64 | 32 (-50%) | 128 (+100%) | 64 (same) |
| Maximum User I/O | 79 | 79 (same) | 79 (same) | 79 (same) |
| fMAX | 118.3 MHz | 118.3 MHz (same) | 118.3 MHz (same) | 118.3 MHz (same) |
| Propagation Delay (tPD) | 7.0 ns | 7.0 ns (same) | 7.0 ns (same) | 7.0 ns (same) |
| Core Voltage | 1.8 V | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) |
| Operating Temperature | -40°C to +125°C (automotive grade) | -40°C to +125°C (automotive grade) | -40°C to +125°C (automotive grade) | -40°C to +100°C (industrial grade) |
| Unit Price (1k qty, as of 2026-09-06) | $3.05 | ~$2.50 (lower) | ~$4.20 (higher) | ~$3.20 (slightly higher) |
Key Differentiators
- Highest density in the MAX V EQFP-64 family at this price point (vs 5M40ZE64A5N)
- Software-only upgrade path to higher density without PCB change (vs 5M160ZE64A5N)
- True 1.8 V core with 3.3 V-tolerant I/O (vs Older MAX II CPLDs (5M40ZE64) at 3.3 V core)
Design Notes
The 5M80ZE64A5N requires a clean 1.8 V core supply (VCCINT, 1.71–1.89 V). Per the MAX V datasheet, VCCINT and VCCIO can be brought up in any order, but the device draws inrush current during flash configuration (~50 mA peak for ≤0.5 ms). Recommended: place a 1 µF X7R ceramic decoupling capacitor within 5 mm of each VCCINT pin and a 0.1 µF + 10 µF bulk cap at the regulator output. For VCCIO banks, use 0.1 µF ceramic bypass on each bank supply pin to minimize simultaneous-switching-noise (SSN) on the I/O ring.
The EQFP-64 package has a 0.5 mm pitch lead-frame with a center thermal pad (per the MAX V datasheet). Recommended PCB layout: 4-layer stackup with continuous ground plane beneath the device, and a 3x3 thermal via array (0.3 mm drill, 0.5 mm pitch) on the center pad tied to the internal GND plane. Route JTAG signals (TCK, TMS, TDI, TDO) with 50 Ω controlled impedance and keep them under 50 mm to avoid reflections. Per the datasheet, leave 4 user I/O reserved for JTAG unless using a separate programmer header.
Common pitfalls with the 5M80ZE64A5N: (1) Do not leave JTAG pins floating - they are dual-purpose I/O and can randomly enter test mode if pulled by noise; tie them to a defined state or use the JTAG header. (2) Do not exceed 3.465 V on any VCCIO bank or 1.89 V on VCCINT - the flash memory will be damaged. (3) When migrating from the 5M40ZE64A5N to the 5M80ZE64A5N, recompile the Quartus project - the bitstream is NOT forward compatible even though the pinout is identical. (4) For automotive designs, use the I-grade variant (5M80ZE64I5N); the A5N suffix denotes -40°C to +125°C automotive range.
Compliance Information
RoHS compliant per Mouser listing. Lead-free and halogen-free per MAX V datasheet. A5N suffix indicates automotive temperature grade (-40°C to +125°C); AEC-Q100 qualification status not explicitly listed in verified data - set as not_applicable pending datasheet confirmation. The I5N variant is industrial grade (-40°C to +100°C).
