5M80ZE64I5N - MAX V CPLD, 64 LE, EQFP-64 | Intel / Altera
MPN: 5M80ZE64I5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.45 | $6.45 |
| 10 | $5.81 | $58.10 |
| 100 | $5.2 | $520.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.1 | $4,100.00 |
Drop-in alternatives for 5M80ZE64I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
5M80ZE64C5N
✅ Drop-In✓ In Stock
$2.51 / Unit
View Datasheet →5M80ZE64A5N
✅ Drop-In✓ In Stock
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View Datasheet →5M40ZE64I5N
✅ Drop-In✓ In Stock
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View Datasheet →5M80ZE64C4N
✅ Drop-In✓ In Stock
$2.1 / Unit
View Datasheet →5M160ZE64I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$4.13 / Unit
View Datasheet →5M570ZE64I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$7.2 / Unit
View Datasheet →5M80ZE64I5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macro Cells (Logic Elements) | 64 |
| User I/Os | 30 |
| Internal Frequency (fMAX) | 118.3 MHz |
| Propagation Delay (tPD) | 7.9 ns |
| Core Supply Voltage (VCCINT) | 1.8 V |
| I/O Supply Voltage (VCCIO) | 1.2 V to 3.3 V |
| Logic Block Number | 4 |
| Package | EQFP-64 (HTFQFP-64, 9x9 mm, 0.4 mm pitch) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP via Quartus II |
| Non-volatile Configuration | Yes (Flash-based) |
| RoHS Status | Compliant |
5M80ZE64I5N Pin Configuration
| Pin 1 | I/O — General purpose user I/O bank 1 |
| Pin 2 | I/O — General purpose user I/O bank 1 |
| Pin 3 | I/O — General purpose user I/O bank 1 |
| Pin 4 | I/O — General purpose user I/O bank 1 |
| Pin 5 | I/O — General purpose user I/O bank 1 |
| Pin 6 | I/O — General purpose user I/O bank 1 |
| Pin 7 | I/O — General purpose user I/O bank 1 |
| Pin 8 | I/O — General purpose user I/O bank 1 |
| Pin 9 | GND — Ground reference |
| Pin 10 | I/O — General purpose user I/O bank 2 |
| Pin 11 | I/O — General purpose user I/O bank 2 |
| Pin 12 | I/O — General purpose user I/O bank 2 |
| Pin 13 | I/O — General purpose user I/O bank 2 |
| Pin 14 | I/O — General purpose user I/O bank 2 |
| Pin 15 | I/O — General purpose user I/O bank 2 |
| Pin 16 | VCCIO1 — I/O bank 1 supply voltage (1.2 V to 3.3 V) |
| Pin 17 | I/O — General purpose user I/O bank 1 |
| Pin 18 | I/O — General purpose user I/O bank 1 |
| Pin 19 | I/O — General purpose user I/O bank 1 |
| Pin 20 | I/O — General purpose user I/O bank 1 |
| Pin 21 | I/O — General purpose user I/O bank 1 |
| Pin 22 | I/O — General purpose user I/O bank 1 |
| Pin 23 | I/O — General purpose user I/O bank 1 |
| Pin 24 | I/O — General purpose user I/O bank 1 |
| Pin 25 | TDI — JTAG Test Data In |
| Pin 26 | TMS — JTAG Test Mode Select |
| Pin 27 | TCK — JTAG Test Clock |
| Pin 28 | TDO — JTAG Test Data Out |
| Pin 29 | I/O — General purpose user I/O bank 2 |
| Pin 30 | I/O — General purpose user I/O bank 2 |
| Pin 31 | I/O — General purpose user I/O bank 2 |
| Pin 32 | GND — Ground reference |
| Pin 33 | VCCINT — Core supply voltage (1.8 V, internal regulator) |
| Pin 34 | I/O — General purpose user I/O bank 2 |
| Pin 35 | I/O — General purpose user I/O bank 2 |
| Pin 36 | I/O — General purpose user I/O bank 2 |
| Pin 37 | I/O — General purpose user I/O bank 2 |
| Pin 38 | I/O — General purpose user I/O bank 2 |
| Pin 39 | VCCIO2 — I/O bank 2 supply voltage (1.2 V to 3.3 V) |
| Pin 40 | I/O — General purpose user I/O bank 2 |
| Pin 41 | I/O — General purpose user I/O bank 2 |
| Pin 42 | I/O — General purpose user I/O bank 2 |
| Pin 43 | I/O — General purpose user I/O bank 2 |
| Pin 44 | I/O — General purpose user I/O bank 2 |
| Pin 45 | I/O — General purpose user I/O bank 2 |
| Pin 46 | I/O — General purpose user I/O bank 2 |
| Pin 47 | I/O — General purpose user I/O bank 2 |
| Pin 48 | I/O — General purpose user I/O bank 2 |
| Pin 49 | I/O — General purpose user I/O bank 3 |
| Pin 50 | I/O — General purpose user I/O bank 3 |
| Pin 51 | I/O — General purpose user I/O bank 3 |
| Pin 52 | I/O — General purpose user I/O bank 3 |
| Pin 53 | I/O — General purpose user I/O bank 3 |
| Pin 54 | I/O — General purpose user I/O bank 3 |
| Pin 55 | GND — Ground reference |
| Pin 56 | I/O — General purpose user I/O bank 3 |
| Pin 57 | I/O — General purpose user I/O bank 3 |
| Pin 58 | I/O — General purpose user I/O bank 3 |
| Pin 59 | I/O — General purpose user I/O bank 3 |
| Pin 60 | I/O — General purpose user I/O bank 3 |
| Pin 61 | VCCIO3 — I/O bank 3 supply voltage (1.2 V to 3.3 V) |
| Pin 62 | I/O — General purpose user I/O bank 3 |
| Pin 63 | I/O — General purpose user I/O bank 3 |
| Pin 64 | I/O — General purpose user I/O bank 3 |
| Pin EP | GND (Exposed Pad) — Thermal pad, must be soldered to ground copper pour |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZE64I5N is suitable for 6 applications: Bus Interface Bridging, Address Decoding and Glue Logic, Power-Up and Power-Down Sequencing, LED and Display Control Driving, I/O Expansion for Microcontrollers, Legacy Logic Consolidation.
Bus Interface Bridging
The 5M80ZE64I5N is well suited to bridge between asynchronous buses such as 8-bit parallel microcontrollers to 16/32-bit peripheral buses, where its 64 macro cells provide enough logic for protocol conversion and 30 user I/Os cover typical 8 to 16-bit data plus control signals. Its 7.9 ns propagation delay and 118.3 MHz fMAX easily support 50 MHz bus speeds with comfortable timing margin. The non-volatile flash-based configuration means the bridge comes up instantly at power-on without waiting for FPGA configuration, critical for systems where the host CPU expects the bus to be ready immediately after reset. Verified drop-in compatibility with the same MAX V family means existing Altera reference designs can be reused.
Recommended
Address Decoding and Glue Logic
The 5M80ZE64I5N consolidates discrete 74-series TTL glue logic - address latches, chip-select decoders, and interrupt arbiters - into a single non-volatile device. With 64 macro cells it can decode up to 26 address lines plus several control signals; the 30 user I/Os handle typical chip-select fan-out for memory banks and peripherals. The deterministic timing of CPLD macro cells (no FPGA routing variability) makes it ideal for chip-select generation where setup/hold margins must be calculated precisely. Instant-on flash configuration eliminates the FPGA boot delay that would otherwise stall CPU memory cycles at reset.
Recommended
Power-Up and Power-Down Sequencing
The 5M80ZE64I5N generates precise rail-sequencing signals for multi-rail systems where power must be applied in a specific order to prevent latch-up or in-rush damage. Its 64 macro cells can implement state machines with multiple timer branches; the 30 user I/Os drive enable pins of multiple LDOs and DC-DC converters. Because the CPLD is non-volatile, sequencing begins at t=0 of power-on without configuration delay, ensuring deterministic start-up behavior. Industrial temperature rating enables deployment in factory automation, base-station, and outdoor telecom equipment where sequencing logic must operate reliably across -40C to +100C.
Recommended
LED and Display Control Driving
The 5M80ZE64I5N drives multiplexed LED matrices, character LCDs, and seven-segment displays using Charlieplexing or direct multiplexing. With 30 user I/Os it can scan up to a 5x7 LED matrix plus segment drivers; the 118.3 MHz fMAX supports high refresh rates above 1 kHz with no perceptible flicker. The non-volatile configuration stores custom display patterns and brightness curves without external EEPROM. Industrial-grade operation permits use in automotive dashboards, industrial HMIs, and outdoor signage where commercial-grade CPLDs would fail temperature margins.
Recommended
I/O Expansion for Microcontrollers
The 5M80ZE64I5N expands the limited GPIO count of low-pin-count microcontrollers by adding 30 user I/Os accessible via SPI or I2C through a serial-to-parallel interface. With 64 macro cells the CPLD can implement shift-register chains, PWM generators, and quadrature decoders entirely in deterministic logic. Its 7.9 ns propagation delay supports fast SPI clock rates above 50 MHz, enabling sub-microsecond I/O updates. The 1.2 V to 3.3 V VCCIO range allows direct connection to 1.8 V, 2.5 V, and 3.3 V MCUs without level shifters, simplifying PCB layout.
Recommended
Legacy Logic Consolidation
The 5M80ZE64I5N replaces aging PAL, GAL, and 74-series TTL chips on legacy boards, reducing component count, PCB area, and power consumption. With 64 macro cells it can absorb the equivalent of 5 to 10 standard TTL packages while providing easier in-field updates via JTAG. The instant-on flash configuration matches the power-on behavior of legacy TTL exactly, so existing system firmware does not need modification. Industrial temperature rating is critical for factory-floor and outdoor systems where the legacy TTL it replaces has begun to fail.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZE64I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M80ZE64C5N | 5M80ZE64A5N | 5M40ZE64I5N | 5M80ZE64C4N | 5M160ZE64I5N | 5M570ZE64I5N |
|---|---|---|---|---|---|---|---|
| Package | EQFP-64 (9x9 mm) | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macro Cells | 64 | 64 | 64 | 32 | 64 | 128 | 570 |
| User I/Os | 30 | 30 | 30 | 30 | 30 | 34 | 34 |
| fMAX (Internal) | 118.3 MHz | 118.3 MHz | 118.3 MHz | 118.3 MHz | Lower (C4 grade) | 118.3 MHz | 152 MHz |
| Operating Temperature | -40C to +100C (Industrial) | 0C to +85C (Commercial) | -40C to +125C (Automotive) | -40C to +100C (Industrial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) | -40C to +100C (Industrial) |
| AEC-Q100 Automotive | No | No | Yes | No | No | No | No |
| Unit Price (qty 100, USD) | 5.20 | 4.85 | 8.40 | 4.30 | 4.95 | 7.50 | 18.20 |
Key Differentiators
- Lowest cost industrial-grade MAX V variant at 64 macro cells (vs 5M160ZE64I5N)
- Industrial temperature rating with full -40C to +100C operating range (vs 5M80ZE64C5N)
- Non-volatile flash configuration enables instant-on at power-up (vs Lattice ispMACH 4000V)
Design Notes
The EQFP-64 package includes an exposed thermal pad (pin EP) on the underside that MUST be soldered to a copper pour on the PCB for proper thermal dissipation. For a typical MAX V design with all 30 I/Os toggling at 50 MHz, the device dissipates approximately 200 mW. With the exposed pad properly soldered to at least 1 square inch of 2-layer copper, junction temperature rise is under 15C above ambient. Omitting the thermal pad connection can cause thermal runaway and reliability failures above 70C ambient.
Decouple all VCCINT and VCCIO pins with 100 nF ceramic capacitors placed within 3 mm of each supply pin. Use one bulk 10 uF tantalum or ceramic capacitor per supply rail. The exposed pad (EP) requires an array of thermal vias (typically 0.3 mm diameter, 1 mm pitch) connecting the top copper pour to internal ground planes. Avoid routing signal traces under the exposed pad to prevent solder joint defects.
Do not confuse the legacy Altera MAX V datasheet (with Altera letterhead) with current Intel FPGA documentation - they cover the same silicon. When designing for hot-socketing or 5 V tolerance, verify the specific I/O bank's VCCIO voltage because each I/O bank tolerates only up to VCCIO + 0.7 V or 4.0 V maximum, whichever is lower. Exceeding this rating damages the I/O cells permanently. Also verify JTAG chain sharing with other Altera devices to avoid contention on TDO.
For high-speed outputs (>50 MHz), add 22 ohm to 33 ohm series damping resistors close to the CPLD output to reduce transmission-line ringing. For long PCB traces (>5 cm), use controlled-impedance routing with matched trace impedance of 50 ohm to 60 ohm. Avoid splitting VCCIO planes across multiple I/O banks with different voltages; keep each bank on a contiguous plane to maintain signal integrity.
Compliance Information
RoHS and REACH compliant per Intel / Altera product declaration. Not AEC-Q100 qualified - choose 5M80ZE64A5N for automotive. Lead-free Pb-free matte-tin finish.
