5M160ZE64C5N - MAX V CPLD, 160 LE, 54 I/O, EQFP-64 | Intel
MPN: 5M160ZE64C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.5 | $9.50 |
| 10 | $8.2 | $82.00 |
| 100 | $6.8 | $680.00 |
| 500 | $5.75 | $2,875.00 |
| 1,000 | $4.95 | $4,950.00 |
Drop-in alternatives for 5M160ZE64C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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5M160ZE64C4N
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View Datasheet β5M160ZE64A5N
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View Datasheet β5M160ZT100C5N
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View Datasheet β5M1270ZF256C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet β5M160ZE64C5N Maximum Ratings & Electrical Characteristics
| Series | MAX V |
| Device Family | MAX V (5M160Z) |
| Logic Elements (LE) | 160 |
| Macrocells | 128 |
| User I/O Pins | 54 |
| Maximum Operating Frequency (fMAX) | 118.3 MHz |
| Pin-to-Pin Logic Delay (tPD) | 1.4 ns (per datasheet) |
| Configuration Memory | Non-volatile Flash |
| Supply Voltage (VCCINT) | 1.8 V |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| User Flash Memory | 8 Kbits |
| Package | 64-pin EQFP (E64) with exposed pad |
| Mounting Type | Surface Mount |
| Operating Temperature | 0Β°C to +85Β°C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) / In-system |
| RoHS Status | Compliant |
| MSL Level | 3 |
5M160ZE64C5N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 4) |
| Pin 51 | I/O β User I/O pin (bank 4) |
| Pin 52 | I/O β User I/O pin (bank 4) |
| Pin 53 | GND β Ground |
| Pin 54 | VCCINT β Core supply voltage (1.8 V) |
| Pin 55 | I/O β User I/O pin (bank 4) |
| Pin 56 | I/O β User I/O pin (bank 4) |
| Pin 57 | I/O β User I/O pin (bank 4) |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | TCK β JTAG test clock input |
| Pin 60 | TMS β JTAG test mode select input |
| Pin 61 | TDI β JTAG test data input |
| Pin 62 | TDO β JTAG test data output |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZE64C5N is suitable for 6 applications: Microcontroller I/O Expansion, Bus Bridge and Level Translator, Power-Up Sequencer for Multi-Rail Systems, Address Decoding and Chip-Select Logic, LED Matrix Driver and Display Multiplexer, Industrial Control Glue Logic.
Microcontroller I/O Expansion
The 5M160ZE64C5N's 54 user I/Os and 1.4 ns pin-to-pin delay make it an excellent GPIO/port-expander companion to low-pin-count MCUs. When a microcontroller running out of pins needs 30-50 extra discrete I/Os for buttons, LEDs, relays, or sensors, the CPLD sits between the MCU and the peripherals. The non-volatile Flash config means the expansion logic is live at power-on - no firmware loader needed - and the 3.3 V LVCMOS I/O bank interfaces directly with common MCU ports without level shifters. Quartus pin planning is straightforward via the MAX V device library.
Recommended
Bus Bridge and Level Translator
The 5M160ZE64C5N bridges incompatible bus protocols (SPI to parallel, I2C to GPIO, UART to memory-mapped register) and translates between 1.8 V, 2.5 V, and 3.3 V logic levels using independent VCCIO banks. Its 118.3 MHz fMAX comfortably exceeds typical SPI (50 MHz) and I2C (3.4 MHz) data rates. The instant-on Flash configuration eliminates the boot delay that complicates bus-bridge design with SRAM FPGAs. Industrial designs use it to connect 5 V legacy peripherals to 1.8 V SoCs via LVCMOS-tolerant I/Os.
Recommended
Power-Up Sequencer for Multi-Rail Systems
The 5M160ZE64C5N is a classic choice for sequencing multiple DC/DC rails in FPGA, ASIC, and SoC power trees. With 160 Logic Elements and 54 I/Os, it can monitor 6-10 PG (power-good) inputs and generate 6-10 EN/SS (enable/soft-start) outputs with programmable delays implemented in Verilog or VHDL. Non-volatile Flash storage means the sequencer is ready at the first millisecond of power-up, with no firmware boot dependency. Industrial servers and telecom line cards rely on this pattern.
Recommended
Address Decoding and Chip-Select Logic
In legacy 8/16/32-bit microcontroller and DSP designs, the 5M160ZE64C5N consolidates address-decoding glue logic - replacing 74HC138, 74HC139, and discrete AND/OR gates with a single programmable decoder. The 1.4 ns tPD is faster than discrete HC-logic propagation chains, and the design can be modified without re-spinning the PCB. The exposed-pad EQFP-64 package handles thermal load comfortably in industrial control backplanes. Quartus schematic capture or HDL entry makes decoder changes a 5-minute job.
Recommended
LED Matrix Driver and Display Multiplexer
With 54 user I/Os, the 5M160ZE64C5N can drive 6-8 rows and 6-8 columns of an LED matrix directly - supporting up to 64-pixel charlieplexed or scanned LED displays without additional driver ICs. The 3.3 V LVCMOS outputs sink/source typical LED currents via series resistors. For larger displays the same CPLD can be the timing controller for external shift registers (74HC595) or LED drivers (TLC5941). The exposed pad keeps the device cool at high PWM refresh rates.
Recommended
Industrial Control Glue Logic
In PLC, motor-control, and industrial sensor-conditioning designs, the 5M160ZE64C5N implements custom encoder interfaces (quadrature decoding, pulse-train multiplication), PWM generators, fault-handling state machines, and watchdog logic. The 160 LE capacity handles typical encoder-plus-PWM-plus-protocol designs in a single chip. Industrial -40Β°C operation is available via the 5M160ZE64I5N drop-in. The exposed-pad package and RoHS compliance meet factory-floor environmental requirements.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZE64C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZE64C4N | 5M160ZE64A5N | 5M160ZE64I5N | 5M160ZT100C5N | 5M1270ZF256C5N |
|---|---|---|---|---|---|---|
| Package | EQFP-64 (E64) | EQFP-64 (E64) - same | EQFP-64 (E64) - same | EQFP-64 (E64) - same | TQFP-100 | FBGA-256 |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 160 | 160 | 160 | 160 | 160 | 1270 |
| User I/O Pins | 54 | 54 | 54 | 54 | 79 | 212 |
| Speed Grade | -5 (118.3 MHz fMAX) | -4 (slower) | -5 | -5 | -5 | -5 |
| Temperature Grade | Commercial 0C to +85C | Commercial | A-grade | Industrial -40C to +100C | Commercial | Commercial |
| Pin-to-Pin Logic Delay (tPD) | 1.4 ns (per datasheet) | [DATA_NEEDED] | [DATA_NEEDED] | 1.4 ns | 1.4 ns | 1.4 ns |
| Configuration Memory | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash | Non-volatile Flash |
| Unit Price (qty 1) | $9.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Lowest-cost 5M160Z E64 variant with -5 speed grade (vs 5M160ZE64I5N)
- Instant-on non-volatile Flash configuration (vs SRAM-based small FPGAs)
- Same 160 LE in smaller E64 footprint (vs 5M160ZT100C5N)
Design Notes
The E64 EQFP package uses a bottom-side exposed pad that MUST be soldered to the PCB ground plane for both thermal dissipation and electrical performance per the Altera 5m160z.pdf pin document. Recommended thermal-via pattern: 5x5 array of 0.3 mm plated-through vias under the pad, connecting to internal ground planes. Without proper thermal connection the junction temperature can rise beyond the 0-85C commercial limit in enclosed industrial enclosures, leading to timing-margin loss or device damage. Estimated: a 0.5W dissipation at 25C ambient will cause ~15C junction rise with proper pad soldering vs >40C rise without.
Decoupling for the 5M160ZE64C5N requires at minimum one 0.1 Β΅F X7R ceramic capacitor placed within 5 mm of each VCCINT pin and one 0.1 Β΅F plus 10 Β΅F bulk capacitor on each VCCIO bank pin. JTAG lines (TCK, TMS, TDI, TDO) should be routed as a bus with matched lengths and pulled up to VCCIO via 10 kΞ© resistors if unused. Keep high-speed I/O traces short and impedance-controlled (50 Ξ© typical for LVCMOS). Reference the MAX V Device Handbook pin-connection guidelines for unused-pin termination.
Do not leave the JTAG pins (TCK/TMS/TDI/TDO) floating - the Altera MAX V datasheet recommends tying TMS and TDI to VCCIO via 10 kΞ© pull-ups and pulling TCK to GND through 10 kΞ© when JTAG is unused, to prevent spurious boundary-scan operations at power-up. All unused user I/Os must be configured as inputs with weak pull-up or output-driving-defined to prevent oscillation. Verify the Quartus pin-out file matches your PCB before programming, and always read back the design via JTAG to confirm configuration integrity after production.
Compliance Information
RoHS and REACH compliant per LCSC and DigiKey compliance listings (2026-09-06). MSL 3 per JEDEC J-STD-033 - floor-life control required after bag opening before reflow. Not AEC-Q100 qualified; the 5M160ZE64I5N is the industrial-temp variant.
