AM6528 Sitara MPU Dual Cortex-A53 + R5F 1.1GHz | TI
MPN: AM6528 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.76 | $18.76 |
| 10 | $17.2 | $172.00 |
| 100 | $15.85 | $1,585.00 |
| 500 | $14.6 | $7,300.00 |
| 1,000 | $13.9 | $13,900.00 |
Drop-in alternatives for AM6528 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
AM6526
β Drop-Inπ Reference alternative (not in catalog)
AM6546
β Drop-Inπ Reference alternative (not in catalog)
AM6548
β Drop-Inπ Reference alternative (not in catalog)
AM6528 Maximum Ratings & Electrical Characteristics
| Core Processor | Arm Cortex-A53 (dual) + Arm Cortex-R5F (dual) |
| Cortex-A53 Max Frequency | 1.1 GHz |
| Cortex-R5F Frequency | 400 MHz |
| Core Count | 4 (2x A53 application + 2x R5F real-time) |
| Data Width | 32-bit |
| Accelerator | 3D GPU (SGX544 graphics acceleration) |
| Industrial Comms Engine | Gigabit PRU-ICSS |
| Family | Sitara AM65x |
| Silicon Revision Shipping | 2.1 |
| Package | 784-FCBGA (23x23 mm) |
| Mounting Type | Surface Mount |
| Supplier Device Package | 784-FCBGA (23x23) |
| Datasheet Document | SPRSP52C (December 2019, revised September 2023) |
AM6528 784-fcbga (23x23) Pin Configuration Guide
Complete pinout information for AM6528 (784-fcbga (23x23) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for AM6528.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
AM6528 is suitable for 6 applications: Industrial HMI Panels, Programmable Logic Controllers (PLCs), Industrial Edge Gateways, Motor Drive Control Systems, Factory Automation Vision Nodes, Building and Infrastructure Controllers.
Industrial HMI Panels
The AM6528 fits graphics-rich human-machine interface panels because its integrated 3D GPU (SGX544-class) renders HMI screens without an external display processor, while the dual Cortex-A53 cores at 1.1 GHz run a Linux stack with Qt or HTML5 UI frameworks. The heterogeneous architecture means UI responsiveness does not degrade the real-time layer: the dual Cortex-R5F cores at 400 MHz run deterministic control and fieldbus tasks in parallel. The Gigabit PRU-ICSS provides industrial Ethernet connectivity for panel-to-controller links. In a typical design the AM6528 drives the display interface, services touch input, and simultaneously bridges to PLC backplanes, with the PRU-ICSS sustaining protocol timing independent of Linux load - a single-chip replacement for MPU-plus-MCU panel architectures.
Recommended
Programmable Logic Controllers (PLCs)
The AM6528 is purpose-built for Industry 4.0 PLC hardware per TI datasheet SPRSP52C. The dual lockstep-capable Cortex-R5F cores at 400 MHz execute the deterministic logic scan and safety-related tasks, while the Cortex-A53 pair at 1.1 GHz runs the Linux-based engineering/runtime environment, web server and OPC UA stack. The Gigabit PRU-ICSS implements EtherCAT, PROFINET and EtherNet/IP slave/master ports with hardware-assisted timing, so fieldbus cycle jitter is decoupled from Linux scheduling. Compared with a discrete MPU+MCU+FPGA PLC stack, the AM6528 collapses the design into one 784-FCBGA device, cutting BOM count and simplifying certification. Designers should follow TI's AM65x GP EVM reference design for DDR4 and power sequencing.
Recommended
Industrial Edge Gateways
For protocol-translation edge gateways, the AM6528 combines Linux-class connectivity (dual Cortex-A53, 1.1 GHz) with protocol-flexible industrial ports via the Gigabit PRU-ICSS, which can be programmed for legacy fieldbuses as well as EtherCAT and PROFINET. The TI family roadmap supports up to 5 Gigabit Ethernet ports with industrial communication software stacks across AM64x/AM65x, per TI's product compare tool. The dual R5F cores handle time-critical packet processing and local control loops, enabling edge analytics and control in one box. Typical deployments bridge OT fieldbuses to MQTT/OPC UA clouds; the A53 cores run containers while the R5F layer guarantees sub-millisecond IO updates. Unit cost around $18.75 (as of 2026-08-30) makes it competitive for mid-range gateway BOMs.
Recommended
Motor Drive Control Systems
In servo drives and industrial motor controllers, the AM6528's dual Cortex-R5F cores at 400 MHz execute current loops and field-oriented control deterministically, while the Cortex-A53 Linux pair hosts drive commissioning software, diagnostics, and fieldbus masters. The Gigabit PRU-ICSS generates/receives encoder and drive-protocol signals (EnDat-style, EtherCAT CoE) with hardware timing that software bit-banging cannot match. The integrated 3D GPU can drive a local drive display or diagnostic panel. Versus a dedicated MCU drive design, this platform adds Linux connectivity and HMI without a second processor; versus an FPGA approach, it keeps development in C/C++ with TI's real-time SDK. Thermal design should target the 784-FCBGA's ground-ball cooling with solid via arrays.
Recommended
Factory Automation Vision Nodes
The AM6528 serves as the processing core for compact machine-vision and inspection nodes where a full PC is excessive. The dual Cortex-A53 cores at 1.1 GHz run Linux image-processing pipelines (OpenCV-based), while the 3D GPU accelerates certain pre/post-processing and HMI overlays. The Gigabit PRU-ICSS and Ethernet subsystems stream results and accept trigger signals with low, deterministic latency handled by the Cortex-R5F cores at 400 MHz. Integration with PLC lines via EtherCAT/PROFINET through the PRU-ICSS removes the need for a separate fieldbus coprocessor. For bandwidth-heavy multi-camera arrays, pair the AM6528 with a TDA4-class vision accelerator on the same platform software stack, keeping the AM6528 as the control and connectivity hub.
Recommended
Building and Infrastructure Controllers
The AM6528 suits building automation controllers, HVAC plant controllers and infrastructure gateways that need both a web-grade Linux interface and hard-real-time I/O. The Cortex-A53 pair runs the BMS application, web dashboard and cloud connectors; the Cortex-R5F cores run the control loop and fail-safe logic; the 3D GPU supports local touch panels. The Gigabit PRU-ICSS can be programmed for industrial and building protocols, and the TI family's up-to-5-Gigabit-Ethernet capability (per the TI compare tool) supports converged IP infrastructures. The 784-FCBGA (23x23 mm) footprint allows a compact controller PCB, and silicon revision 2.1 availability (datasheet SPRSP52C) plus active lifecycle status ensures long-term sourcing for multi-year building programs.
Recommended
Recommended Products Summary
Engineering reference data for AM6528 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AM6526 | AM6546 | AM6548 |
|---|---|---|---|---|
| Package | 784-FCBGA (23x23 mm) | 784-FCBGA (23x23 mm) - same | 784-FCBGA (23x23 mm) - same | 784-FCBGA (23x23 mm) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Cortex-A53 Cores | 2 (up to 1.1 GHz) | 2 | 4 | 4 |
| Cortex-R5F Cores | 2 at 400 MHz | 2 at 400 MHz | 2 at 400 MHz | 2 at 400 MHz |
| Gigabit PRU-ICSS | Yes | Yes | Yes | Yes |
| 3D Graphics | Yes (SGX544-class GPU) | [DATA_NEEDED] | [DATA_NEEDED] | Yes |
| Target Tier in AM65x Family | Mid-tier (dual A53) | Entry dual A53 | Quad A53 | Top-tier quad A53 |
| Datasheet Document | SPRSP52C | SPRSP52C (same document) | SPRSP52C (same document) | SPRSP52C (same document) |
Key Differentiators
- Balanced cost/performance mid-tier position (vs AM6548)
- Graphics capability in the same footprint (vs AM6526)
- Upgradability within one footprint (vs AM6546)
Design Notes
The 784-ball FCBGA (23x23 mm, ~0.8 mm pitch class) requires a controlled-impedance multilayer stackup, typically at least 8-10 layers with dedicated DDR4 and power planes. Plan BGA escape routing (dogleg or via-in-pad) before finalizing the outer ball ring assignments. Always start from TI's AM65x GP EVM layout as a proven reference for DDR4 length matching and power tree placement; re-deriving the stackup from scratch is the most common cause of first-silicon signal-integrity failures on this package.
AM65x platforms use a multi-rail power tree (core, GPU, DDR, IO rails) with mandatory power sequencing. TI's reference designs pair the processor with a dedicated PMIC; replicating the sequencing with discrete regulators requires verifying each rail's ramp order against the datasheet power-up requirements in SPRSP52C. Estimated: rail-count errors most often surface as boot failures rather than damage, so validate sequencing on the EVM first. Keep core rail decoupling exactly as the reference design; do not reduce bulk capacitance without measurement.
Silicon revision matters: TI datasheet SPRSP52C covers silicon revision 2.1, and earlier-revision errata do not apply to rev 2.1 silicon. When sourcing second-hand or long-tail inventory, verify the silicon revision marking before release, since software (U-Boot, kernel device trees) may encode revision-specific workarounds. Also confirm the exact orderable suffix (e.g., AM6528BACDXEA) against your footprint, as AM65x speed grades and temperature grades map to different order codes on the same 784-FCBGA package.
Compliance Information
Compliance status was not stated in the provided verified web data; consult TI's product page at ti.com/product/AM6528 for current RoHS/REACH certification data.
