5M570ZT100C5N - MAX V 570 LEs CPLD, 100-TQFP | Intel / Altera
MPN: 5M570ZT100C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.58 | $5.58 |
| 10 | $5.2 | $52.00 |
| 100 | $4.65 | $465.00 |
| 500 | $4.1 | $2,050.00 |
| 1,000 | $3.7 | $3,700.00 |
Drop-in alternatives for 5M570ZT100C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M570ZT100C4N
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View Datasheet β5M570ZT100A5N
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View Datasheet β5M160ZT100C5N
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View Datasheet β5M570ZT100C5N Maximum Ratings & Electrical Characteristics
| Series | MAX V |
| Logic Elements | 570 |
| Macrocells | 440 |
| Number of I/O Pins | 74 |
| Maximum Operating Frequency | 118.3 MHz |
| Pin-to-Pin Delay (tPD) | 17.7 ns |
| Core Supply Voltage | 1.8 V |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V (LVCMOS, LVTTL, PCI 3.3 V) |
| Program Memory Type | Flash (non-volatile) |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) |
| User Flash Memory | 1.6 Kbits |
| Operating Temperature Range | 0C to +85C (commercial) |
| Package | TQFP-100 (16 x 16 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount |
| RoHS Status | Lead Free (per FindIC listing) |
5M570ZT100C5N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | GND β Ground |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 31 | TMS β JTAG Test Mode Select |
| Pin 32 | TCK β JTAG Test Clock |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | I/O β User I/O pin (bank 3) |
| Pin 45 | GND β Ground |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 4) |
| Pin 50 | I/O β User I/O pin (bank 4) |
| Pin 51 | I/O β User I/O pin (bank 4) |
| Pin 52 | I/O β User I/O pin (bank 4) |
| Pin 53 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 54 | I/O β User I/O pin (bank 4) |
| Pin 55 | I/O β User I/O pin (bank 4) |
| Pin 56 | I/O β User I/O pin (bank 4) |
| Pin 57 | I/O β User I/O pin (bank 4) |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | I/O β User I/O pin (bank 4) |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | TDO β JTAG Test Data Out |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | VCCINT β Core supply voltage (1.8 V) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 1) |
| Pin 75 | I/O β User I/O pin (bank 1) |
| Pin 76 | I/O β User I/O pin (bank 1) |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β User I/O pin (bank 1) |
| Pin 79 | I/O β User I/O pin (bank 1) |
| Pin 80 | I/O β User I/O pin (bank 1) |
| Pin 81 | I/O β User I/O pin (bank 1) |
| Pin 82 | I/O β User I/O pin (bank 1) |
| Pin 83 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 84 | I/O β User I/O pin (bank 1) |
| Pin 85 | I/O β User I/O pin (bank 1) |
| Pin 86 | I/O β User I/O pin (bank 1) |
| Pin 87 | I/O β User I/O pin (bank 1) |
| Pin 88 | I/O β User I/O pin (bank 1) |
| Pin 89 | I/O β User I/O pin (bank 1) |
| Pin 90 | I/O β User I/O pin (bank 1) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin (bank 1) |
| Pin 93 | I/O β User I/O pin (bank 1) |
| Pin 94 | I/O β User I/O pin (bank 1) |
| Pin 95 | I/O β User I/O pin (bank 1) |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | I/O β User I/O pin (bank 1) |
| Pin 100 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M570ZT100C5N is suitable for 6 applications: Microcontroller I/O Expansion, PCI 3.3 V Bus Interface Bridge, Industrial Control and Power Sequencing, Glue-Logic Replacement, LED Display and Signage Controllers, Consumer Electronics and IoT Bridges.
Microcontroller I/O Expansion
The 5M570ZT100C5N adds 74 user I/Os to a microcontroller that has too few pins for its peripheral set. With 570 logic elements and 1.8 V/2.5 V/3.3 V/5.0 V multi-voltage I/O support, the device translates between a 1.8 V Cortex-M0+ MCU and 5 V legacy peripherals in a single chip, eliminating external level shifters. The non-volatile flash configuration means the I/O map is retained across power cycles, enabling instant-on pin assignment without boot firmware. Quartus II designs compile to a JIC/JAM bitstream loaded over JTAG in minutes, making hardware bring-up fast. Trade-off: at 118.3 MHz fMAX the device is fast enough for parallel bus multiplexing (address latch, chip-select decode) but is not intended for high-speed SERDES.
Recommended
PCI 3.3 V Bus Interface Bridge
The MAX V family datasheet explicitly states that the 5M570ZT100C5N is compliant with PCI Local Bus Specification Revision 2.2 3.3 V electrical specifications, making it suitable as a glue-logic bridge between a host CPU and a PCI slot. With 440 macrocells the device can implement a full PCI arbiter, target decoder, and configuration register in one chip. The 17.7 ns tPD is well within the 33 MHz PCI clock budget for combinational decoding paths. Engineers typically instantiate the device in TQFP-100 when the PCB already routes a PCI bus to a legacy ASIC or FPGA companion. This avoids the cost of an FPGA plus external boot PROM.
Recommended
Industrial Control and Power Sequencing
The 5M570ZT100C5N's deterministic pin-to-pin timing (17.7 ns) and instant-on flash configuration make it well-suited for industrial power-supply sequencers and discrete-logic replacements on PLC backplanes. It can implement multi-rail power-up/down state machines, watchdog timers, and fault latches without firmware dependencies, surviving brown-out events that would crash a soft-core microcontroller. With 100 I/O available on the TQFP-100 footprint, the device can interface to 24 V optocoupler-isolated inputs and 5 V relay drivers in parallel. Industrial control engineers often choose this part when the certification path forbids software on a general-purpose MCU. Trade-off: no embedded analog, so ADC and current sensing still need an external analog front end.
Recommended
Glue-Logic Replacement
The 5M570ZT100C5N replaces dozens of 74-series TTL gates (HC/HCT/LV) with a single programmable device, simplifying PCB layout and reducing assembly cost. With 570 logic elements and 440 macrocells, the device absorbs address decoding, chip-select generation, and interrupt steering in legacy 8/16-bit microcomputer boards. The non-volatile flash configuration removes the need for a configuration EEPROM, and the 1.8 V core with multi-voltage I/O means the part can sit on a board that mixes 3.3 V and 5 V logic domains. Designers migrating from discrete glue logic reuse the Quartus II schematic capture flow and get free simulation. Trade-off: a discrete-logic board is cheaper at very low complexity (<20 gates), so use this part when you cross the 50-100 gate threshold.
Recommended
LED Display and Signage Controllers
The 5M570ZT100C5N drives multiplexed LED matrices and seven-segment displays, with up to 74 user I/Os available for row/column scanning and PWM dimming. The 17.7 ns tPD supports row refresh rates above 1 kHz for flicker-free video-rate dimming on small panels. Designers use the device to generate precise timing signals (OE, LAT, CLK) for shift-register-driven LED drivers such as TLC5941 or WS2801, offloading the timing-critical patterns from a host MCU. The flash-based, instant-on behavior is valuable in signage that must boot in <100 ms. Trade-off: brightness/color levels are not hardware-accelerated, so animations above ~60 Hz need a faster MCU or FPGA.
Recommended
Consumer Electronics and IoT Bridges
The 5M570ZT100C5N bridges low-speed sensor buses (I2C, SPI, UART) to application processors in consumer devices, replacing discrete level shifters and custom ASICs. Its 1.8 V core plus 1.8 V/2.5 V/3.3 V/5.0 V I/O bank support allows direct connection to 5 V sensors and 1.8 V SoCs without external translators. With 570 LEs and 1.6 Kbits of user flash, the part can implement wake-up logic that holds the SoC in reset until sensor power-rails are stable. The TQFP-100 footprint is hand-solderable for prototype boards. Trade-off: the MAX V device does not include hard IP for I2C/SPI - those controllers are synthesized in soft logic, so designers must verify timing closure at the target clock.
Recommended
Recommended Products Summary
Engineering reference data for 5M570ZT100C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M570ZT100C4N | 5M570ZT100A5N | 5M570ZT100C5 | 5M240ZT100C5N | 5M160ZT100C5N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 (16x16 mm, 0.5 mm pitch) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Logic Elements | 570 | 570 | 570 | 570 | 240 (-58%) | 160 (-72%) |
| Macrocells | 440 | 440 | 440 | 440 | 192 (-56%) | 128 (-71%) |
| Speed Grade | C5 (118.3 MHz / 17.7 ns tPD) | C4 (slower than 17.7 ns) | A5 (slowest) | C5 - identical | C5 (same grade) | C5 (same grade) |
| User I/O Pins | 74 | 74 | 74 | 74 | 79 | 79 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V (MAX II) | 1.8 V (MAX II) |
| Series / Family | MAX V | MAX V | MAX V | MAX V | MAX II (older) | MAX II (older) |
Key Differentiators
- Highest speed grade within MAX V 570 LE family in TQFP-100 (vs 5M570ZT100C4N)
- Non-volatile flash configuration = instant-on at power-up (vs SRAM-based small FPGAs)
- Multi-voltage I/O banks (1.8/2.5/3.3/5.0 V) on a single device (vs 5M160ZT100C5N (MAX II))
Design Notes
The 5M570ZT100C5N requires two supply rails: VCCINT = 1.8 V for the core logic and VCCIO1-VCCIO4 for each of the four I/O banks. VCCIO can be independently set to 1.8 V, 2.5 V, 3.3 V, or 5.0 V depending on the connected peripherals. Decoupling: place one 100 nF X7R ceramic capacitor as close as possible to each VCCIO and VCCINT pin, and add a single 10 uF bulk capacitor near the device for transient suppression. Estimated: at 118.3 MHz internal operation across 74 I/Os switching at moderate toggle rates, typical ICCINT is in the low tens of mA - verify with the datasheet power estimator before finalizing the LDO/DCDC budget.
Route JTAG signals (TCK, TMS, TDI, TDO) as a short, contiguous group with a 33 ohm series-termination resistor on TDO if the trace exceeds 50 mm. Keep the JTAG chain away from clock and switching-power traces to avoid coupling noise into TCK that can cause programming failures. The TQFP-100 0.5 mm pitch package requires careful land-pattern design per IPC-7351 - the exposed pad is the GND paddle and must be soldered for thermal dissipation even though the MAX V is a low-power device. Recommended: 4-layer board with a dedicated ground plane on layer 2 directly under the device to minimize loop inductance on the VCCINT/VCCIO decoupling capacitors.
When using the device at the PCI 3.3 V electrical level, the MAX V datasheet specifies a maximum pin-to-pin delay of 17.7 ns - this is well within the 33 MHz PCI clock period (30 ns) for combinational decode paths but leaves little margin for synchronous logic at one PCI clock. Designers should simulate worst-case paths in Quartus II TimeQuest at the slow-corner model to confirm 33 MHz timing closure. Drive strength: each output pin supports programmable slew rate (slow/fast) and PCI-compliant drive strength - select slow slew rate on heavily loaded buses to limit dV/dt and ground bounce.
Compliance Information
Lead-free per FindIC listing. RoHS/REACH compliant per the same. No AEC-Q100 variant in the MAX V family - choose MAX II industrial temperature for harsh environments.
