EP1810JI-35 - 48-Macrocell Classic EPLD, 35ns | Intel / Altera
MPN: EP1810JI-35 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $21.95 | $10,975.00 |
| 1,000 | $18.6 | $18,600.00 |
Drop-in alternatives for EP1810JI-35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP1810JC-35
β Drop-Inβ In Stock
$5.48 / Unit
View Datasheet βEP1810JC-45
β Drop-Inβ In Stock
$21.1 / Unit
View Datasheet βEP1810GC-35
β Drop-Inβ In Stock
$177.12 / Unit
View Datasheet βEP1810GC-35AB
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP1810GM883B
β Drop-Inβ In Stock
$125.4 / Unit
View Datasheet βEP1810GM/883B
β Drop-Inβ In Stock
$49.75 / Unit
View Datasheet βEP1810GI-45
β Drop-Inβ In Stock
$56.4 / Unit
View Datasheet βEP1810JI-35 Maximum Ratings & Electrical Characteristics
| Device Family | Classic EPLD |
| Macrocells | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells |
| Dedicated Inputs | 48 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns |
| Speed Grade | -35 |
| Package | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | CMOS EPROM (UV-erasable) |
| Operating Temperature | -40C to +85C (Industrial) |
| Supply Voltage | 5 V (typical classic EPLD) |
| Programmability | UV-erase, windowed for lab reprogram |
| Mounting Type | Through-Hole (J-lead) |
| Programming Interface | JEDEC fuse file via legacy programmer |
EP1810JI-35 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (LAB A) |
| Pin 2 | I/O β Bidirectional I/O pin (LAB A) |
| Pin 3 | I/O β Bidirectional I/O pin (LAB A) |
| Pin 4 | I/O β Bidirectional I/O pin (LAB A) |
| Pin 5 | I/O β Bidirectional I/O pin (LAB A) |
| Pin 6 | I/O β Bidirectional I/O pin (LAB A) |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β Bidirectional I/O pin (LAB B) |
| Pin 9 | I/O β Bidirectional I/O pin (LAB B) |
| Pin 10 | I/O β Bidirectional I/O pin (LAB B) |
| Pin 11 | β Bidirectional I/O pin (LAB B) |
| Pin 12 | I/O β Bidirectional I/O pin (LAB B) |
| Pin 13 | I/O β Bidirectional I/O pin (LAB B) |
| Pin 14 | CLK β Global clock input |
| Pin 15 | VCC β +5 V supply |
| Pin 16 | I/O β Bidirectional I/O pin (LAB C) |
| Pin 17 | I/O β Bidirectional I/O pin (LAB C) |
| Pin 18 | I/O β Bidirectional I/O pin (LAB C) |
| Pin 19 | I/O β Bidirectional I/O pin (LAB C) |
| Pin 20 | I/O β Bidirectional I/O pin (LAB C) |
| Pin 21 | I/O β Bidirectional I/O pin (LAB C) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β Bidirectional I/O pin (LAB D) |
| Pin 24 | I/O β Bidirectional I/O pin (LAB D) |
| Pin 25 | I/O β Bidirectional I/O pin (LAB D) |
| Pin 26 | I/O β Bidirectional I/O pin (LAB D) |
| Pin 27 | I/O β Bidirectional I/O pin (LAB D) |
| Pin 28 | I/O β Bidirectional I/O pin (LAB D) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810JI-35 is suitable for 6 applications: Microprocessor Address Decoding, TTL/74LS Glue Logic Replacement, Peripheral Controller (ISA/VME Bus), State-Machine and Sequencer Implementation, Legacy Industrial Control Systems, Test and Measurement Instrumentation.
Microprocessor Address Decoding
The EP1810JI-35's 48 macrocells and 35 ns tPD make it well suited for legacy microprocessor address-decoding tasks where a deterministic combinational delay is required. With 48 dedicated inputs it can decode a full 24-bit address bus in a single device, producing chip-select outputs in 35 ns - fast enough for 8 MHz 80286 and 12 MHz 68030-era designs. The industrial temperature grade (-40C to +85C) supports factory-floor and outdoor enclosures, and the UV-erasable window allows design-iteration without component waste. Compare against a 74LS138 decoder tree: one EP1810JI-35 replaces six to ten TTL packages, cutting board area by roughly 60 percent while improving noise margin.
Recommended
TTL/74LS Glue Logic Replacement
Designers frequently select the EP1810JI-35 to consolidate scattered 74LS series glue logic into a single programmable device. The 48 macrocells can implement dozens of AND/OR/XOR gates with registered outputs, replacing entire boards of small-scale and medium-scale TTL. The 35 ns tPD matches typical 74LS244/374 propagation delays, ensuring timing closure without redesign of downstream state machines. Industrial temperature grade and the ceramic windowed package suit long-lifecycle defense and aerospace platforms that must remain in service for 20+ years and where the original part number is locked by qualification documents.
Recommended
Peripheral Controller (ISA/VME Bus)
The EP1810JI-35 was a common peripheral controller on legacy ISA and VME bus architectures, where its 48 macrocells implemented bus arbitration, interrupt handling, and register decode logic. The 35 ns tPD pairs well with 8 MHz ISA timing and the deterministic macrocell delay avoids metastability that discrete TTL occasionally exhibits. The ceramic JLCC windowed package withstands vibration and thermal cycling in industrial enclosures, and the device can be reprogrammed in-circuit via legacy programmers, which simplifies field-upgrade logistics for installed VME systems.
Recommended
State-Machine and Sequencer Implementation
Each EP1810JI-35 macrocell contains a programmable flip-flop with product-term clock and reset, allowing efficient state-machine synthesis. Up to 48 registered outputs can implement multiple concurrent state machines such as motor-control sequencers, communication-protocol handlers, or test-instrument timing generators. The 35 ns tPD sets the worst-case combinational path, while registered outputs deliver clean, glitch-free state transitions at clock rates up to approximately 25 MHz. The windowed ceramic package supports iterative state-table refinement during prototype development.
Recommended
Legacy Industrial Control Systems
Long-lifecycle industrial controllers (SCADA RTUs, PLCs, CNC interfaces) designed in the late 1980s and early 1990s frequently used EP1810-family EPLDs as glue logic. The EP1810JI-35's industrial temperature range, 35 ns delay, and through-hole JLCC package match those legacy boards exactly. Maintenance engineers stocking spare parts for 20+ year-old systems rely on obsolete-component distributors for this part because redesign to a modern MAX II CPLD would require a full PCB re-spin and re-certification of the controller, which is rarely economically viable.
Recommended
Test and Measurement Instrumentation
Bench-top test instruments built around VXIbus or GPIB backplanes often used EP1810JI-35 parts to implement handshake logic, address decoders, and timing generators. The deterministic 35 ns delay provides predictable instrument response times, while the UV-erasable window lets the original instrument manufacturer update personality modules without component scrap. Maintaining these instruments today requires drop-in EP1810-family replacements sourced from franchised obsolete-stock distributors, since re-engineering to a modern CPLD would invalidate the instrument's calibration history.
Recommended
Recommended Products Summary
Engineering reference data for EP1810JI-35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810JC-35 | EP1810JC-45 | EP1810GC-35 | EP1810GC-35AB | EP1810GM883B |
|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | JLCC-28 (ceramic, windowed) | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same | JLCC-28 (ceramic windowed) - same |
| Pin-to-Pin Delay (tPD) | 35 ns | 35 ns | 45 ns (slower, +28%) | 35 ns | 35 ns | [DATA_NEEDED: speed grade on MIL variant] |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Military (-55C to +125C) |
| MIL-STD-883 Screening | No | No | No | No | Yes (883B) | Yes (883B) |
| Logic Array Blocks | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells | 8 LABs x 16 macrocells |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade in ceramic windowed package (vs EP1810JC-35)
- Faster speed grade at same industrial temperature (vs EP1810GI-45)
- MIL-spec screening available with same die (vs EP1810GC-35)
Design Notes
The EP1810JI-35 is an obsolete part with no remaining franchised production. New inventory must be sourced from authorized obsolete-stock distributors; counterfeits are common in the secondary market. Always insist on a Certificate of Conformance (CoC) and decapsulation/verification report for aerospace and defense applications, since ceramic windowed JLCC packages are frequently remarked from pull-stock.
The 28-pin JLCC footprint has a 1.27 mm (50 mil) pitch and uses J-leads that wrap under the ceramic body. PCB land diameter should be 1.0 mm with a 0.2 mm solder mask expansion to allow hand-rework and socket insertion. A 28-pin JLCC socket (e.g., 3M or Aries) is recommended for development to allow UV erasure and reprogramming.
Estimated: at 5 V supply and 100% I/O toggle at 25 MHz, the EP1810JI-35 dissipates approximately 0.5 W. The ceramic JLCC package provides excellent thermal conductivity to the PCB; still, derate I/O toggle rate by 20% in enclosed industrial enclosures above 70C to maintain junction temperature within the -40C to +85C industrial range.
Route the global clock pin (pin 14) with a guarded trace and 50 ohm characteristic impedance. Place a 100 nF decoupling capacitor within 5 mm of the VCC pin (pin 15) and a second 10 uF bulk capacitor near the supply entry point. Tie both GND pins (7 and 22) directly to the ground plane with short, wide traces.
Compliance Information
EP1810JI-35 is an obsolete ceramic-windowed EPLD; modern RoHS/REACH declarations are not typically issued. For new designs, choose a MAX II/MAX V CPLD for full RoHS/REACH compliance.
