Intel

EP20K100CB356C7ES - APEX20K 100K Gate FPGA | Intel | 356-BGA

MPN: EP20K100CB356C7ES ✗ End of Life

In Stock Ships in 1-3 business days

1.8 V Vdss 356-BGA Package C7 Speed 53,248 Memory

From $92 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$145	$145.00
10	$132	$1,320.00
100	$118	$11,800.00
500	$105	$52,500.00
1,000	$92	$92,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EP20K100CB356C7ES Overview

The Intel EP20K100CB356C7ES is a member of the APEX20K family of SRAM-based, multi-standard FPGAs, integrating 263,000 gates (100,000 typical gates, 4,160 logic elements) with 252 user I/O pins in a 356-ball BGA package. This industrial-grade device delivers flexible programmable logic with built-in ES (Embedded System) features, targeting high-performance DSP and datapath-intensive designs.

An FPGA (Field-Programmable Gate Array) is a semiconductor device containing configurable logic blocks (CLBs), programmable interconnects, and I/O cells that can be re-programmed after manufacturing. APEX20K belongs to the FPGA -> programmable logic -> logic device hierarchy of digital ICs. Unlike ASICs, FPGAs offer rapid prototyping and in-system reprogrammability, making them essential for telecommunications, video processing, and embedded computing platforms where design iteration speed matters.

Key features of the EP20K100CB356C7ES include 4,160 logic elements, 26,560 typical logic gates, 53,248 maximum system gates, 53,248 RAM bits of embedded memory, and 252 user I/O pins supporting multiple I/O standards such as LVTTL, LVCMOS, PCI, and GTL+. The device operates from a 1.8 V core supply with 3.3 V/2.5 V I/O compatibility and includes on-chip PLL clock management.

Architecturally, the APEX20K combines a four-input look-up table (LUT) structure with embedded array blocks (EABs) for memory and specialized arithmetic functions. The C7 speed grade offers a balance of timing margin and power consumption for industrial and commercial applications. The device is configured via JTAG (IEEE 1149.1) or passive serial configuration with configuration bitstream stored in external PROM.

Typical applications include telecommunications switching, broadband access equipment, video broadcast and image processing, industrial motor control, and DSP co-processing in medical imaging. With its high I/O count and embedded memory, the EP20K100CB356C7ES is well suited for multi-channel data acquisition and protocol bridging designs.

When designing with the APEX20K family, pay close attention to power sequencing - the core 1.8 V supply must ramp before I/O supplies to avoid latch-up. The Quartus development toolchain (legacy MAX+PLUS II for older designs) supports this device, providing synthesis, place-and-route, and timing analysis. Use surface-mount BGA assembly with proper thermal vias to dissipate the device's 1.5-2 W typical power.

This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.

Drop-in alternatives for EP20K100CB356C7ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K100CB356C7ES (same form factor and footprint) — differing in Process Technology, Package, Speed Grade, Family, Mounting Type.

EP20K100BC356-1

Intel

Process Technology: 0.15 micrometer all-layer copper CMOS

Speed Grade: -1

Mounting Type: Surface Mount