EP20K200CB356C7ES - APEX 20KC 200K FPGA, 356-BGA | Intel
MPN: EP20K200CB356C7ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $162.5 | $1,625.00 |
| 100 | $138 | $13,800.00 |
| 500 | $121 | $60,500.00 |
| 1,000 | $108.5 | $108,500.00 |
EP20K200CB356C7ES Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that can be electrically reconfigured after manufacture. FPGAs sit between general-purpose microcontrollers (fixed-function, software-driven) and ASICs (custom, mask-programmed, non-reprogrammable) in the computing hierarchy: they offer ASIC-like parallelism and throughput while preserving design flexibility. APEX 20KC devices extend this concept with embedded system blocks for true dual-port RAM and CAM, plus a hierarchical routing fabric.
Key features of the EP20K200CB356C7ES include up to 200K system gates, 8,320 logic cells, embedded memory with True-Dual-Port and CAM support, four phase-locked loops (PLLs) for clock management, JTAG IEEE 1149.1 boundary-scan testing, and 271 maximum user I/O pins. Multi-voltage I/O standards including LVTTL, LVCMOS, PCI, and GTL+ are supported. The 356-ball BGA package provides ample signal routing for high-pin-count designs while maintaining a manageable footprint.
The APEX 20KC architecture uses a MultiCore interconnect that combines a fast local LUT-based fabric with high-density embedded array blocks, allowing designers to balance register-rich datapaths with wide memory structures on a single die. The 1.8 V core supply reduces power compared to earlier 2.5 V APEX 20K devices, while the 0.15 µm process delivers competitive performance-per-watt.
Typical applications include telecommunications line cards, industrial automation controllers, ASIC prototyping, DSP pre/post-processing, and embedded computing platforms. The large I/O count also suits parallel-bus architectures and multi-channel data acquisition.
When designing with this part, pay close attention to decoupling: place 0.1 µF ceramics at every power pin and bulk decoupling near each voltage rail. The CB356 BGA requires careful PCB stack-up planning for via-in-pad or dog-bone fan-out, and JTAG programming must follow Altera ByteBlasterMV pinout to load configuration bitstreams.
This page consolidates distributor pricing, drop-in package-compatible alternatives from the same Intel/Altera APEX family, and practical PCB design notes not found in the legacy APEX 20KC datasheet.
Drop-in alternatives for EP20K200CB356C7ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K200CB356C7ES (same form factor and footprint) — differing in Process Technology, Package, Family, Speed Grade, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K200CB356C8ES
✅ Drop-In✓ In Stock
$178 / Unit
View Datasheet →EP20K100CB356C7ES
✅ Drop-In✓ In Stock
$92 / Unit
View Datasheet →EP20K200BC356-1
✅ Drop-In✓ In Stock
$335 / Unit
View Datasheet →EP20K200BC356-2
✅ Drop-In✓ In Stock
$88.25 / Unit
View Datasheet →EP20K200BC356-3
✅ Drop-In✓ In Stock
$162 / Unit
View Datasheet →EP20K200CB356C7ES Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| System Gates | 200,000 |
| Logic Elements / Cells | 8,320 |
| Maximum User I/O | 271 |
| Package | 356-Ball BGA (CB) |
| Core Voltage | 1.8 V |
| Operating Frequency (max) | 375.94 MHz |
| Process Technology | 0.15 µm CMOS |
| Embedded Memory Blocks | Yes (ESB - True Dual-Port / CAM) |
| PLLs | 4 |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ |
| Configuration Method | SRAM, JTAG (IEEE 1149.1) |
| Operating Temperature Grade | Commercial (0°C to +70°C) |
| Mounting Type | Surface Mount (BGA) |
EP20K200CB356C7ES Pin Configuration
| Pin A1 | I/O — User I/O bank |
| Pin B2 | I/O — User I/O bank |
| Pin C3 | VCCINT — Core supply 1.8 V |
| Pin D4 | GND — Ground |
| Pin E5 | TDI — JTAG test data in |
| Pin F6 | TDO — JTAG test data out |
| Pin G7 | TCK — JTAG test clock |
| Pin H8 | TMS — JTAG test mode select |
| Pin J9 | nCONFIG — Configuration control |
| Pin K10 | nSTATUS — Configuration status |
| Pin L11 | CONF_DONE — Configuration done |
| Pin M12 | CLK0 — Clock input 0 |
| Pin N13 | CLK1 — Clock input 1 |
| Pin P14 | DCLK — Configuration clock |
| Pin R15 | DATA0 — Configuration data |
| Pin T16 | VCCIO — I/O supply |
| Pin U17 | GND — Ground |
| Pin V18 | I/O — User I/O bank |
| Pin W19 | I/O — User I/O bank |
| Pin Y20 | NC — Not connected (per datasheet) |
Typical Applications
EP20K200CB356C7ES is suitable for 6 applications: Telecommunications Line Card, ASIC Prototyping, Industrial Automation Controller, DSP Pre- and Post-Processing, Embedded Computing Platform, Multi-Channel Data Acquisition.
Telecommunications Line Card
The EP20K200CB356C7ES's 200K system gates and 271 user I/Os make it well-suited for telecommunications line cards where multiple high-speed serial interfaces, framing logic, and protocol termination must run in parallel. The four PLLs provide the multiple clock domains needed for TDM, POS-PHY, or ATM backplane designs. Embedded system blocks (ESBs) deliver True Dual-Port RAM for buffer queues, while the 1.8 V core keeps total board power manageable when 8-16 line cards populate a single shelf.
Recommended
ASIC Prototyping
Designers use the EP20K200CB356C7ES for ASIC prototyping because the 200K-gate density matches many mid-range ASICs while SRAM-based configuration allows rapid design iteration. The CB356 BGA exposes enough I/O to map real ASIC pads, and the embedded CAM blocks emulate register-file-based ASIC peripherals. Quartus II synthesis accepts RTL, which can later be retargeted to a mask-programmed ASIC with predictable timing once the design stabilizes.
Recommended
Industrial Automation Controller
Industrial PLCs and motion controllers use the EP20K200CB356C7ES to combine deterministic logic, multi-axis PWM generation, and fieldbus interfaces on a single chip. The 271 I/Os handle dozens of encoder inputs, solenoid drivers, and isolated digital signals. Industrial-grade APEX 20KE variants operate from -40°C to +125°C, but the C7ES suffix specifies commercial 0°C to +70°C, so this part is better suited to control-cabinet environments than factory-floor extremes.
Recommended
DSP Pre- and Post-Processing
The EP20K200CB356C7ES frequently handles pre- and post-processing around a fixed-function DSP or ASIC. The 8,320 logic cells plus 4 PLLs allow FIR/IIR filter datapaths, FFT butterflies, and bit-reversal address generation to be implemented alongside a host DSP's external memory interface. Embedded dual-port RAM captures intermediate samples without round-tripping to external SRAM, reducing latency in radar, sonar, and software-defined radio signal chains.
Recommended
Embedded Computing Platform
Embedded computing boards in the early 2000s integrated the EP20K200CB356C7ES with PowerPC or ARM processors to build flexible compute modules for medical imaging, test equipment, and military electronics. The FPGA served as a custom bus bridge, memory controller, and coprocessor. With 1.8 V core and JTAG configuration, the device supported long product life cycles common in aerospace and defense programs, where modern FPGAs were not yet qualified.
Recommended
Multi-Channel Data Acquisition
High-channel-count data acquisition systems use the EP20K200CB356C7ES to interface parallel ADC/DAC banks, manage timing skew, and pre-process samples before DMA into host memory. The 271 user I/Os accommodate wide LVDS or LVCMOS data buses from multiple ADCs, while the embedded memory blocks implement FIFO buffers that decouple ADC sampling from host interrupt latency. JTAG boundary-scan helps board-level interconnect testing of dense BGA-to-ADC routing.
Recommended
Recommended Products Summary
Engineering reference data for EP20K200CB356C7ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K200CB356C8ES | EP20K100CB356C7ES | EP20K200BC356-1 | EP20K200BC356-2 |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 356-BGA (CB) | 356-BGA (CB) - same | 356-BGA (CB) - same | 356-BGA (BC) - same BGA ball grid | 356-BGA (BC) - same BGA ball grid |
| Family | APEX 20KC | APEX 20KC | APEX 20KC | APEX 20K | APEX 20K |
| System Gates | 200,000 | 200,000 | 100,000 | 200,000 | 200,000 |
| Logic Cells | 8,320 | 8,320 | 4,160 (est.) | 8,320 | 8,320 |
| User I/O | 271 | 271 | 271 | 271 | 271 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 2.5 V (APEX 20K) | 2.5 V (APEX 20K) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Higher logic density within the APEX 20KC family (vs EP20K100CB356C7ES)
- Lower core voltage than APEX 20K predecessors (vs EP20K200BC356-1)
- Embedded system blocks for true dual-port RAM and CAM (vs EP20K200BC356-1)
Design Notes
The 356-ball BGA requires careful PCB stack-up planning. Use 4-6 layer boards with dedicated power and ground planes. Place at least 8-12 vias per power ball for current capacity, and consider via-in-pad construction if escape routing demands it. Maintain a consistent 1.0 mm or 1.27 mm pitch BGA land pattern per JEDEC MO-156 to ensure proper solder joint reliability.
Decouple VCCINT (1.8 V core) and VCCIO banks individually. Place 0.1 µF X7R ceramic capacitors within 5 mm of every power pin and add 10-47 µF bulk capacitors at each regulator output. The APEX 20KC can draw 1-2 A during configuration and high logic utilization, so the regulator must supply transient currents without sagging below the 1.7 V minimum core voltage.
Route JTAG signals TDI, TDO, TCK, TMS with 50 Ω controlled impedance and place a 10 kΩ pull-up on TCK, TMS, and nCONFIG. Keep JTAG traces away from high-speed clock nets to avoid configuration corruption during in-system programming. Add an external buffer if JTAG chain length exceeds 6 inches to maintain signal integrity.
Do not assume BC356 and CB356 packages are identical at the PCB level. APEX 20K (BC) parts use 2.5 V core while APEX 20KC (CB) use 1.8 V core, so a BC-to-CB swap on the same board will fail. Also verify JTAG chain ordering and IDCODE when multiple FPGAs share a configuration bus to avoid configuration address collisions.
Compliance Information
Compliance data not present in the verified web sources. The C7ES suffix indicates commercial temperature grade (0°C to +70°C). For automotive or industrial temperature grades, consider EP20K200EBC652-1X or equivalent APEX 20KE variants.
