EP20K400FC672-4 - APEX 20K FPGA 400K Gates 672-BBGA | Intel
MPN: EP20K400FC672-4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132.5 | $1,325.00 |
| 100 | $118.2 | $11,820.00 |
| 250 | $108.75 | $27,187.50 |
| 500 | $99.4 | $49,700.00 |
EP20K400FC672-4 Overview
An FPGA (Field-Programmable Gate Array) is a type of programmable logic device that allows designers to configure digital logic after manufacturing. Within the broader semiconductor taxonomy, FPGAs belong to programmable logic devices -> digital ICs -> integrated circuits. The APEX 20K family pioneered the combination of LUT-based logic and embedded memory in a single fabric, predating the modern Stratix/Cyclone families and serving as a stepping stone to today's heterogeneous SoC FPGAs.
The EP20K400FC672-4 delivers up to 400,000 typical gates (roughly 212,992 logic elements per the -1 variant datasheet), 212,992 system gates, 16640 logic elements, and 502 Kbits of embedded memory distributed across the embedded system blocks. Per the verified distributor and datasheet records, the device carries a Moisture Sensitivity Level (MSL) of 3 and a peak reflow rating of 220 C, consistent with surface-mount BGA assembly.
Applications for this part span legacy communications infrastructure, industrial control, ASIC prototyping, and glue-logic replacement on legacy boards where the design has been validated against APEX 20K timing models. The 672-pin BGA package supplies abundant user I/O for memory interfaces and parallel bus expansion. Designers working with this part typically rely on the Altera/Intel Quartus II design environment (legacy support). Note that the APEX 20K family has been classified NRND/EOL by Intel in favor of newer Cyclone/Stratix devices, so availability should be verified before starting new designs. The page below combines distributor pricing, equivalent APEX 20K alternatives, and design notes not synthesized in any single manufacturer document.
Drop-in alternatives for EP20K400FC672-4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FC672-4 (same form factor and footprint) — differing in Speed Grade, Package, Family, Operating Temperature, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FC672-3
✅ Drop-In✓ In Stock
$138 / Unit
View Datasheet →EP20K400FC672-2
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400FC672-1XGZ
✅ Drop-In✓ In Stock
$195 / Unit
View Datasheet →EP20K400FC672-3X
✅ Drop-In✓ In Stock
$152.4 / Unit
View Datasheet →EP20K400FC672-3V
✅ Drop-In✓ In Stock
$152 / Unit
View Datasheet →EP20K400FC672-4 Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Device Logic Elements | 16640 |
| Typical Gates | 400000 |
| System Gates | 212992 |
| Embedded Memory (Kbits) | 502 |
| Speed Grade | -4 (slowest) |
| Package | 672-BBGA (FC) |
| Mounting Type | Surface Mount |
| Moisture Sensitivity Level (MSL) | 3 |
| Peak Reflow Temperature | 220 C |
| RoHS Status | unknown |
| REACH Status | unknown |
| Lead-Free | unknown |
| Process Technology | MultiCore (LUT + ESB) |
| Design Tool | Quartus II (legacy) |
EP20K400FC672-4 672-bbga (fc) Pin Configuration Guide
Pin configuration for EP20K400FC672-4 (672-bbga (fc) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FC672-4.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FC672-4 is suitable for 6 applications: Legacy Communications Backplane Logic, ASIC Prototyping and Emulation, Industrial Control and Factory Automation, Medical Imaging Front-End Processing, Military and Aerospace Avionics Bus Interfaces, Test and Measurement Instrumentation.
Legacy Communications Backplane Logic
The EP20K400FC672-4 was widely deployed in telecom backplane glue logic, channelized TDM/Ethernet bridges, and SONET/SDH framing equipment in the late 1990s and early 2000s. Its 502 Kbits of embedded system block memory, combined with 16640 logic elements and 672 user I/O balls, was sufficient to implement multi-port bridges, HDLC controllers, and ATM segmentation-and-reassembly engines. The MultiCore fabric allowed designers to place dense FIFOs directly in the ESB without consuming LUTs, while the high I/O count supported wide parallel buses to ASICs and framers. For legacy long-life-cycle programs (defense, aerospace sustainment, telecom refurbishment) where the design has been validated against the APEX 20K timing model, this part remains the only qualified solution and is sourced via the authorized aftermarket.
Recommended
ASIC Prototyping and Emulation
With ~400 K typical gates and 502 Kbits of distributed memory, the EP20K400FC672-4 served as an ASIC prototype vehicle for mid-complexity ASICs (100K-300K gate ASICs). Its LUT-based fabric, predictable interconnect delay, and JTAG-based configuration allowed design teams to validate RTL before tape-out. The 672-BBGA package delivered the I/O bandwidth necessary to map wide on-chip buses to external test equipment. Quartus II supported full APEX 20K timing simulation, and the MultiCore architecture was a closer match to ASIC gate-array timing than earlier pure-LUT FPGAs. Today the part is still used by sustainment programs to emulate legacy ASICs whose fab masks are no longer available, and the BGA package simplifies rework on existing prototyping boards.
Recommended
Industrial Control and Factory Automation
The APEX 20K family was adopted in industrial PLC, motor drive, and machine-vision controller designs thanks to its abundant combinational logic for state machines and PID loops, plus ESB memory for sensor-data buffering. The EP20K400FC672-4 in particular was used in multi-axis motion controllers where its 16640 logic elements could implement several axis-control state machines in parallel, while its 672-BGA I/O supported simultaneous encoder inputs, PWM outputs, and fieldbus interfaces (Profibus, DeviceNet). The 1.8 V core with 3.3 V-tolerant I/O simplified interface to legacy 5 V drivers via external resistors. MSL 3 and 220 C peak reflow remain compatible with standard SMT lines used in industrial electronics manufacturing.
Recommended
Medical Imaging Front-End Processing
In the early 2000s the EP20K400FC672-4 was deployed in ultrasound and CT imaging front-end boards, where its ESB memory acted as line buffers for scan conversion and its LUT fabric implemented FIR/IIR filter banks. The 502 Kbits of memory was ideal for buffering one or two scan lines at a time, and the 672-BGA package enabled dense routing of high-speed ADC data lanes. Although newer Cyclone/Stratix families offer LVDS transceivers and DSP blocks better suited to modern imaging, many installed medical systems (subject to FDA lifecycle validation) cannot be redesigned, so the EP20K400FC672-4 remains the qualified part for field replacements on installed bases.
Recommended
Military and Aerospace Avionics Bus Interfaces
The APEX 20K family, including EP20K400FC672-4, was qualified into several MIL-STD-1553, ARINC 429, and avionics data concentrator designs in the late 1990s. Its robust BGA package, wide operating temperature range when derated appropriately, and JTAG boundary-scan support simplified board-level test. The 672-ball BGA supplied enough I/O to implement multiple redundant bus interfaces plus discrete I/O for discrete avionics signals. For defense sustainment programs where the original FPGA design has been formally qualified and cannot be re-engineered, this part remains procurable through QML/VQML distributors and aftermarket brokers holding bonded inventory.
Recommended
Test and Measurement Instrumentation
The EP20K400FC672-4 was used as the central controller in logic analyzers, protocol testers, and ATE (Automatic Test Equipment) platforms. Its high I/O count supported parallel capture of wide digital buses, while ESB memory stored captured frames. The LUT fabric implemented protocol-state decoders for I2C, SPI, UART, and parallel bus standards. Quartus II allowed incremental recompile during test program development. Although modern instrumentation has migrated to PXIe/USB-based FPGAs (Cyclone, Kintex), many installed ATE racks cannot be redesigned without recertification, so the EP20K400FC672-4 remains the qualified logic element for legacy test heads.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FC672-4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FC672-3 | EP20K400FC672-2 | EP20K400FC672-1 | EP20K400FC672-3X | EP20K400FC672-3V |
|---|---|---|---|---|---|---|
| Package | 672-BBGA (FC) | 672-BBGA (FC) - same | 672-BBGA (FC) - same | 672-BBGA (FC) - same | 672-BBGA (FC) - same | 672-BBGA (FC) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Speed Grade | -4 (slowest) | -3 (faster) | -2 (faster) | -1 (fastest) | -3 | -3 |
| Logic Elements | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 |
| Embedded Memory (Kbits) | 502 | 502 | 502 | 502 | 502 | 502 |
| Typical Gates | 400000 | 400000 | 400000 | 400000 | 400000 | 400000 |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Drop-In Compatible | N/A (target part) | Yes (same FC672 BGA, pin-for-pin) | Yes (same FC672 BGA, pin-for-pin) | Yes (same FC672 BGA, pin-for-pin) | Yes (same FC672 BGA, pin-for-pin) | Yes (same FC672 BGA, pin-for-pin) |
Key Differentiators
- Same package, same die, faster speed grade (vs EP20K400FC672-3)
- Slowest commercial speed grade - cost-optimized (vs EP20K400FC672-1)
- Integrated ESB memory reduces external SRAM need (vs Cyclone IV E (EP4CE40F23))
Design Notes
The 672-ball FineLine BGA package requires a 4-6 layer PCB with continuous power and ground planes under the BGA. Use 0.5 mm ball pitch escape routing with microvias (laser-drilled preferred). Decoupling: place 0.1 uF X7R ceramic caps within 2 mm of every VCCINT/VCCIO ball pair, plus bulk 10-47 uF tantalum or polymer caps at the PCB edge. BGA requires X-ray inspection post-reflow because the joints are hidden under the package.
APEX 20K I/O rise/fall times at 3.3 V are in the 1-2 ns range, producing moderate SSO/EMI. For designs with >32 simultaneous-switching outputs, use spread-spectrum clocking and add 33 ohm series-termination resistors at the driver. For high-speed (>100 MHz) parallel buses, simulate with IBIS models (available in the APEX 20K IBIS library) and target 50 ohm controlled impedance on the PCB. The LVDS capability is limited compared to modern Cyclone/Stratix parts.
Do not assume EP20K400FC672-4 is still in production - Intel/Altera has classified the APEX 20K family NRND/EOL. Stock at authorized distributors is limited to remaining inventory and authorized aftermarket brokers; lead times can stretch to 8-12 weeks. For new designs, migrate to Cyclone IV E (EP4CE series) or Cyclone 10 LP (10CL series), which are active, lower-power, lower-cost, and supported by current Quartus Prime software.
Compliance Information
Compliance status not present in the verified web data; consult the manufacturer datasheet or product page for definitive RoHS/REACH/lead-free information. APEX 20K is a programmable logic IC, not an automotive-grade part, so AEC-Q100 is not applicable.
