EP20K400FC672-3V - 400K Gates APEX 20K FPGA 672-FBGA | Altera
MPN: EP20K400FC672-3V ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $280 | $280.00 |
| 10 | $245 | $2,450.00 |
| 100 | $195 | $19,500.00 |
| 500 | $168 | $84,000.00 |
| 1,000 | $152 | $152,000.00 |
EP20K400FC672-3V Overview
An FPGA (Field-Programmable Gate Array) is a programmable logic device containing an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that engineers can configure after manufacture to implement arbitrary digital logic. FPGAs sit within the broader semiconductor hierarchy as a sub-category of programmable logic devices (PLDs), themselves part of the logic IC family. The APEX 20K family was one of the first PLDs to combine LUT logic with embedded system blocks (ESBs) that double as dual-port RAM, ROM, or CAM, enabling system-on-a-programmable-chip (SOPC) integration.
Key features of the EP20K400FC672-3V include 16,640 logic elements (cells), 212,992 bits of embedded memory, 502 user I/O, MultiCore architecture with embedded system blocks, in-system programmability via IEEE 1149.1 JTAG, and 5 V tolerant I/O with PCI-compliant drivers. The device supports up to 167 MHz internal operation and is suitable for high-density glue-logic, bus-interface, and datapath-replacement designs.
Typical applications for the EP20K400FC672-3V include telecommunications line-card controllers, high-speed data-path bridge logic, industrial control backplanes, PCI/PCI-X bus interfaces, and legacy ASIC prototyping. Engineers select this part when a large LUT/embedded-memory fabric is required on a single 5 V tolerant device with proven APEX toolchain support.
When designing with this device, observe Vccint decoupling per the APEX 20KC datasheet (DS-APEX20K-5.1): use 0.1 µF and 0.01 µF ceramic capacitors close to every Vccint/Vss pair, and provide a minimum of eight 0.2 µF bulk capacitors around the package perimeter. Signal-integrity simulations are recommended above 100 MHz to control simultaneous-switching noise across the 502 I/O.
This page synthesizes distributor pricing, drop-in same-package alternatives from the Site MPN list, and practical design notes that are not found on the manufacturer datasheet alone.
Drop-in alternatives for EP20K400FC672-3V — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FC672-3V (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Process Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400EFC672-3
✅ Drop-In✓ In Stock
$199.5 / Unit
View Datasheet →EP20K400EFC672-3N
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFC672-2X
✅ Drop-In✓ In Stock
$118.9 / Unit
View Datasheet →EP20K400EFC672-2N
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400EFC672-2
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K400EFC672-1
✅ Drop-In✓ In Stock
$110 / Unit
View Datasheet →EP20K400FC672-3V Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Series | APEX-20KC |
| Device Type | FPGA (Field Programmable Gate Array) |
| Logic Elements / Cells | 16640 |
| System Gates | 400000 |
| Total RAM Bits | 212992 |
| Number of I/O | 502 |
| Number of LABs/CLBs | 1664 |
| Number of Logic Elements | 16640 |
| Supply Voltage (Core) | 1.71 V to 1.89 V |
| Mounting Type | Surface Mount |
| Package / Case | 672-BBGA, FCBGA |
| Supplier Device Package | 672-FBGA (27x27) |
| Process Technology | 0.22 µm |
| Maximum Internal Frequency | 167 MHz (typical) |
| Pin-to-Pin Delay | 3.6 ns |
| Speed Grade | -3 |
| Programmability Type | In-system (JTAG IEEE 1149.1) |
EP20K400FC672-3V 672-fbga (27x27) Pin Configuration Guide
Pin configuration for EP20K400FC672-3V (672-fbga (27x27) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FC672-3V.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FC672-3V is suitable for 6 applications: Telecommunications Line-Card Controller, PCI / PCI-X Bus Interface Bridge, Industrial Control Backplane Logic, Legacy ASIC Prototyping, High-Speed Datapath Replacement, Military and Aerospace Avionics Interfaces.
Telecommunications Line-Card Controller
The EP20K400FC672-3V fits telecom line-card designs because its 16,640 logic elements and 212,992 bits of embedded RAM are large enough to implement TDM bus arbiters, framer interfaces, and HDLC controllers on a single device. The 502 user I/O comfortably route 32-bit wide parallel data buses plus multiple serial links without external mux logic. At the -3 speed grade's 167 MHz internal maximum, the part meets typical 155 MHz telecom backplane rates with margin. Designers place it between the line interface unit and the switch fabric ASIC, using the embedded system blocks as elastic FIFOs for clock-domain crossing. Unlike newer Cyclone parts, the APEX 20KC is the lowest-risk replacement for legacy line cards already in field service for decades.
Recommended
PCI / PCI-X Bus Interface Bridge
The EP20K400FC672-3V is well suited to PCI and PCI-X bridge applications because it offers 5 V tolerant I/O and PCI-compliant drivers per the APEX 20KC datasheet. The 502 user I/O can simultaneously host a 64-bit PCI-X bus plus secondary local-bus expansion. Its 16,640 logic elements absorb the typical 8K to 12K gates of a PCI-to-local-bridge state machine plus DMA engines, and the 212 Kbit of embedded memory serves as scatter-gather descriptor RAM. At 167 MHz, the device comfortably meets the 133 MHz PCI-X target with timing margin. Designers select this part when migrating a legacy 5 V tolerant system to a single-chip bridge without resorting to multiple CPLDs.
Recommended
Industrial Control Backplane Logic
The EP20K400FC672-3V fits industrial backplane controllers because its 672-ball FBGA and 502 I/O support the dense parallel busses of VME, CompactPCI, and proprietary industrial backplanes. The MultiCore architecture lets one device replace several legacy 74LS series glue-logic chips while adding in-system reprogrammability for field upgrades. Its -40 °C to +85 °C industrial temperature grade (when ordered as such) suits factory-floor environments. The 3.6 ns pin-to-pin delay allows timing closure on 50 MHz backplanes without aggressive pipelining. Designers use it as a glue-logic consolidation device to reduce BOM count and PCB area in long-life industrial platforms.
Recommended
Legacy ASIC Prototyping
The EP20K400FC672-3V is a strong fit for ASIC prototyping because its 400K system gates and 16,640 logic elements with embedded system blocks mirror the LUT-plus-memory fabric of mid-complexity ASICs. Engineers targeting a 0.18 µm or 0.13 µm ASIC can partition their design across one or two APEX 20KC devices to validate RTL before tape-out. The 167 MHz internal maximum lets the prototype run near-ASIC speeds for software validation. Quartus II synthesis provides ASIC-friendly constraints that port directly to standard-cell flows. Designers choose this part when they need a programmable platform that emulates the timing and resource profile of an actual ASIC.
Recommended
High-Speed Datapath Replacement
The EP20K400FC672-3V is used in high-speed datapath replacement applications where a discrete ASIC or gate-array must be substituted with a programmable device without losing throughput. Its 16,640 logic elements and 212 Kbit of dual-port RAM can implement wide datapath functions such as CRC engines, Reed-Solomon codecs, and protocol translators. The -3 speed grade's 167 MHz and 3.6 ns pin-to-pin delay provide sufficient timing margin for multi-gigabit serial interfaces when paired with external SERDES. Designers choose this part when they want to consolidate multiple legacy datapath ICs into one programmable device for inventory simplification.
Recommended
Military and Aerospace Avionics Interfaces
The EP20K400FC672-3V is suitable for military and aerospace interface modules that require high logic density in a rugged surface-mount package. Its 502 I/O support the many parallel sensor buses (MIL-STD-1553, ARINC 429) and discrete I/O found in avionics LRUs. The MultiCore architecture lets one device implement multiple independent bus monitors on a single chip, reducing unit cost and weight. Long-term support from Rochester Electronics and authorized distributors makes it a viable choice for programs with 10 to 20 year field-life requirements. Designers use it for retrofit programs where the original APEX 20KC design must be reproduced exactly.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FC672-3V — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400EFC672-3 | EP20K400EFC672-3N | EP20K400EFC672-2X | EP20K400EFC672-2N | EP20K400EFC672-2 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-FBGA (27x27) | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same | 672-FBGA (27x27) - same |
| Family | APEX 20KC | APEX 20KE | APEX 20KE | APEX 20KE | APEX 20KE | APEX 20KE |
| Speed Grade | -3 (167 MHz) | -3 (167 MHz) | -3 (167 MHz) | -2 (~150 MHz) | -2 (~150 MHz) | -2 (~150 MHz) |
| Logic Elements | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 |
| Total RAM Bits | 212992 | 212992 | 212992 | 212992 | 212992 | 212992 |
| User I/O | 502 | 502 | 502 | 502 | 502 | 502 |
| Core Voltage | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V |
Key Differentiators
- Highest speed grade available for the 400K-gate 672-FBGA APEX 20KC (vs EP20K400EFC672-2X)
- Largest APEX 20K-family density in 672-FBGA with embedded system blocks (vs EP20K400EBC652-3)
- MultiCore architecture combining LUT and product-term logic (vs EP20K200EFC672-2)
Design Notes
Estimated: APEX 20KC Iccint at 167 MHz with 50% toggle rate on a typical 16K LE design is approximately 1.5 A from a 1.8 V supply (~2.7 W). Apply eight 0.2 µF X7R ceramic decoupling capacitors evenly around the 672-FBGA perimeter plus one 22 µF tantalum bulk capacitor per the DS-APEX20K-5.1 reference decoupling schematic. Each Vccio bank requires its own 0.1 µF + 10 µF pair, sized for the bank's switching load.
Estimated: with 2.7 W core dissipation and the 672-FBGA's typical θJA of 18 °C/W (27x27 mm, JEDEC EIA/JESD51 still-air test board), junction temperature rises about 49 °C above ambient. For ambient of 70 °C in an industrial enclosure, junction reaches ~119 °C, still below the 125 °C maximum. Add a thermal pad or forced-air cooling if ambient exceeds 70 °C or if your design achieves >60% utilization and >100 MHz operation.
Route the four-layer stackup as signal/ground/power/signal with continuous power planes under the 672-BGA. Use 0.5 mm pitch escape routing on the top layer and via-in-pad for inner balls. Apply a solid Vccint polygon on the inner layer adjacent to the device and stitch the GND plane with 1.0 mm pitch vias around the BGA perimeter to provide a low-impedance return path for the high-speed MultiCore interconnect.
Do NOT confuse the EP20K400FC672-3V (1.8 V Vccint, APEX 20KC) with the EP20K400FC672-3 (2.5 V Vccint, APEX 20K). They share the 672-FBGA pinout but the core voltage rail is incompatible. Always verify the 'V' suffix before board bring-up. Also, never hot-swap the JTAG chain while Vccint is below 1.7 V because partial programming can latch the device into an unknown state; cycle power to recover.
For designs operating above 100 MHz on the 502 I/O, perform IBIS simulation on the APEX 20KC output buffers and use series termination matching 50 Ω to 65 Ω traces. Avoid simultaneous switching of more than 20 outputs per bank; if more switching is required, stagger the clocks using the device's programmable delay elements. Reference AN 192 (Altera Application Note 192) for APEX 20KC simultaneous-switching noise guidance.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status not stated in verified web data; APEX 20KC family pre-dates RoHS enforcement. N-suffixed variants (e.g., EP20K400EFC672-3N) typically indicate lead-free terminal finish. Always request a material declaration from the authorized distributor for production compliance verification.