EP2S90F1020I5N - Stratix II FPGA 90,960 LE | Intel / Altera
MPN: EP2S90F1020I5N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1450 | $1,450.00 |
| 10 | $1390 | $13,900.00 |
| 100 | $1320 | $132,000.00 |
| 500 | $1245 | $622,500.00 |
| 1,000 | $1180 | $1,180,000.00 |
EP2S90F1020I5N Overview
A Field Programmable Gate Array (FPGA) is a reprogrammable semiconductor device built from an array of configurable logic blocks (CLBs), dedicated DSP blocks, embedded memory blocks, and programmable I/O cells, all wired together via a programmable interconnect fabric. Within the broader taxonomy, FPGAs belong to programmable logic devices (PLDs), a sibling category to CPLDs (Complex Programmable Logic Devices); PLDs in turn are a subfamily of digital integrated circuits under the broader semiconductor umbrella. The Stratix II family introduced the adaptive logic module (ALM) architecture that doubled effective logic capacity per LUT versus the original Stratix generation.
Key features of the EP2S90F1020I5N include approximately 4.5 Mbits of embedded RAM, up to 12 transceiver channels supporting data rates up to 1 Gbps, dedicated DSP blocks for high-speed multiplication and accumulation, and 1020-ball FineLine BGA packaging optimized for high-pin-count PCB routing. The industrial temperature grade (-40C to +100C ambient at the case) supports deployment in harsh-environment industrial systems. Up to 8 PLLs provide flexible clock management and synthesis for multi-rate system designs.
Architecturally, the Stratix II ALM combines an 8-input adaptive look-up table with two dedicated adders, allowing a single ALM to implement a full 3-input adder plus a 4-input LUT without performance penalty. The TriMatrix memory subsystem provides three on-chip memory block sizes (M512, M4K, M-RAM) optimized for different buffer and register-file needs, and dedicated hardware multipliers support 18x18 signed multiplication in a single DSP block cycle.
Typical applications include high-throughput digital signal processing for wireless baseband and radar, ASIC prototyping and emulation, high-speed serial protocol bridging (PCI Express, Serial RapidIO, Gigabit Ethernet), software-defined radio (SDR) front-ends, and high-performance image processing pipelines. The combination of high logic density, embedded transceivers, and DSP blocks makes it well-suited to designs that previously required discrete processors plus glue logic.
When designing with this device, careful attention must be paid to power-integrity analysis because the EP2S90F1020I5N can draw several watts of core current at full utilization; a multi-rail decoupling network with low-impedance bulk capacitors is required, and thermal management must be planned using the published theta-JA and theta-JC values. Designers should also use the Quartus II design software (the design entry toolchain supported by the Stratix II family) to validate pin assignments and timing closure before PCB layout.
This page synthesizes distributor pricing from Octopart, drop-in compatible Stratix II speed-grade and package alternatives, and practical design notes that extend beyond the manufacturer datasheet to accelerate board bring-up and supply-chain decision making.
Drop-in alternatives for EP2S90F1020I5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1020I5N (same form factor and footprint) — differing in Package, Operating Temperature, Speed Grade, Mounting Type, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F1020I4N
✅ Drop-In✓ In Stock
$1995 / Unit
View Datasheet →EP2S90F1020I4
✅ Drop-In✓ In Stock
$2200 / Unit
View Datasheet →EP2S90F1020I4GA
✅ Drop-In✓ In Stock
$220 / Unit
View Datasheet →EP2S90F1020I3N
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EP2S90F1020C5N
✅ Drop-In✓ In Stock
$1240 / Unit
View Datasheet →EP2S90F1020C5
✅ Drop-In✓ In Stock
$1450 / Unit
View Datasheet →EP2S90F1020I5N Maximum Ratings & Electrical Characteristics
| Series | Stratix II |
| Logic Elements | 90,960 |
| Total RAM Bits | 4,520,448 (approx. 4.5 Mbits) |
| Transceiver Channels | Up to 12 |
| Transceiver Data Rate (max) | 1 Gbps per channel |
| Number of PLLs | 8 |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm CMOS |
| Package | 1020-ball FineLine BGA (FBGA) |
| Operating Temperature | -40C to +100C (industrial) |
| Speed Grade | 5 |
| Mounting Type | Surface Mount |
EP2S90F1020I5N Pin Configuration
| Pin A1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin A2 | VCCIO — I/O bank supply |
| Pin A3 | GND — Ground |
| Pin B1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin B2 | VCC — Core supply (1.2 V) |
| Pin B3 | GND — Ground |
| Pin C1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin C2 | VCCIO — I/O bank supply |
| Pin C3 | GND — Ground |
| Pin D1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin D2 | VCC — Core supply (1.2 V) |
| Pin D3 | GND — Ground |
| Pin E1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin E2 | VCCIO — I/O bank supply |
| Pin E3 | GND — Ground |
| Pin F1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin F2 | VCC — Core supply (1.2 V) |
| Pin F3 | GND — Ground |
| Pin G1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin G2 | VCCIO — I/O bank supply |
| Pin G3 | GND — Ground |
| Pin H1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin H2 | VCC — Core supply (1.2 V) |
| Pin H3 | GND — Ground |
| Pin J1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin J2 | VCCIO — I/O bank supply |
| Pin J3 | GND — Ground |
| Pin K1 | IO — User I/O bank (assigned per pin connection guidelines) |
| Pin K2 | VCC — Core supply (1.2 V) |
| Pin K3 | GND — Ground |
Typical Applications
EP2S90F1020I5N is suitable for 7 applications: ASIC Prototyping and Emulation, High-Speed Serial Protocol Bridging, Wireless Baseband Signal Processing, Software-Defined Radio (SDR) Front-End, High-Performance Image Processing, Industrial Control and Automation, Radar Signal Processing.
ASIC Prototyping and Emulation
The EP2S90F1020I5N's 90,960 logic elements and 1020-ball FBGA package make it well-suited to ASIC prototyping and emulation, where designers map multi-million-gate ASICs into one or several Stratix II devices. The industrial speed grade I5 supports clock rates typically needed for bring-up of large SoCs. The Quartus II software integrates with the Altera MegaWizard Plug-In Manager and supports incremental compile to keep design iterations fast. Pair the device with JTAG-based configuration via the EPC16 or EPCS configuration device for in-system reprogramming.
Recommended
High-Speed Serial Protocol Bridging
With up to 12 embedded transceiver channels at 1 Gbps each, the EP2S90F1020I5N supports high-speed serial protocol bridging for PCI Express Gen1, Serial RapidIO, Gigabit Ethernet, and custom serial links. The Stratix II transceivers integrate 8b/10b encoding and word-alignment logic, reducing the soft-logic footprint required by competing FPGA families. Place the device adjacent to physical-layer magnetics or SFP cages with controlled-impedance routing. This design pattern suits telecom line cards and storage bridging applications.
Recommended
Wireless Baseband Signal Processing
The EP2S90F1020I5N's dedicated 18x18 hardware multipliers and TriMatrix memory blocks deliver high-throughput DSP performance for wireless baseband signal processing. The 90,960 logic elements and abundant DSP blocks enable multi-channel filter chains, FFT cores, and channelization tasks typical of LTE and WiMAX baseband designs. The industrial temperature grade allows deployment in outdoor base-station equipment. The 1.2 V core minimizes power dissipation in densely packed baseband line cards.
Recommended
Software-Defined Radio (SDR) Front-End
The combination of high logic density, embedded transceivers, and DSP blocks in the EP2S90F1020I5N makes it a strong match for software-defined radio front-ends where digital downconversion, channelization, and modulation are all performed in the FPGA. The 1 Gbps transceivers handle raw ADC data streaming, while the 18x18 multipliers accelerate FIR filtering and FFT operations. Industrial temperature grade supports portable and field-deployable SDR systems. The Quartus II DSP Builder tool accelerates fixed-point algorithm development.
Recommended
High-Performance Image Processing
The EP2S90F1020I5N's high logic density and embedded memory suit high-performance image processing pipelines such as real-time video enhancement, machine-vision pre-processing, and medical imaging front-ends. The on-chip TriMatrix memory buffers multi-megapixel frames without external SRAM, and the DSP blocks accelerate convolution and morphological operators. The 1020-ball FBGA provides sufficient user I/O for parallel camera interfaces including LVDS and sub-LVDS. Industrial temperature grade supports medical and industrial imaging deployments.
Recommended
Industrial Control and Automation
The EP2S90F1020I5N's industrial temperature range (-40C to +100C) and high logic density make it appropriate for industrial control and automation systems, including motion controllers, PLC co-processors, and high-speed deterministic networking fabrics. The PLLs support multi-rate servo loops and the embedded transceivers carry real-time Ethernet or EtherCAT traffic. The 1020-ball FBGA supports the dense multi-protocol I/O typical of industrial controllers. Pair with industrial-grade EEPROM for configuration storage in factory-floor environments.
Recommended
Radar Signal Processing
The EP2S90F1020I5N serves radar signal-processing front-ends where pulse compression, moving-target indication (MTI), and constant-false-alarm-rate (CFAR) algorithms demand high DSP throughput. The 18x18 hardware multipliers accelerate matched-filter convolutions, and the 4.5 Mbits of on-chip RAM store range-Doppler maps across multiple coherent processing intervals. The 1 Gbps transceivers accept digitized IF streams from high-speed ADCs. Industrial temperature grade supports deployment in airborne and maritime radar systems.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1020I5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1020I4N | EP2S90F1020I4 | EP2S90F1020I3N | EP2S90F1020C5N |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 1020-ball FBGA | 1020-ball FBGA - same | 1020-ball FBGA - same | 1020-ball FBGA - same | 1020-ball FBGA - same |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Speed Grade | I5 (industrial, slowest) | I4 (faster) | I4 (faster) | I3 (fastest industrial) | C5 (commercial, slowest) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Process Technology | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
| Packaging Option | N (lead-free) | N (lead-free) | Tray (no N suffix) | N (lead-free) | N (lead-free) |
Key Differentiators
- Slowest industrial speed grade - lowest cost in the family (vs EP2S90F1020I4N)
- Industrial temperature range - harsh-environment capable (vs EP2S90F1020C5N)
- Largest 1020-ball FBGA in the Stratix II family (vs EP2S60F1020I4N)
Design Notes
Estimated: At full utilization, the EP2S90F1020I5N core can draw several amps from the 1.2 V rail. Use the Quartus II PowerPlay analyzer with your design's toggle rate and utilization to size the regulator. A multi-rail decoupling network with low-impedance bulk capacitors, plus per-pin high-frequency 0.1 uF and 0.01 uF decoupling placed close to each power ball, is mandatory. Add a power-supply bulk capacitor of at least 470 uF low-ESR near the device to absorb transient inrush during configuration.
The 1020-ball FineLine BGA package relies on PCB copper for heat dissipation. Design the PCB with at least four inner copper plane layers stitched with thermal vias under the BGA's central thermal balls to provide a low thermal-resistance path to a heatsink or cold plate. Estimate: at 10 W dissipation and theta-JA near 5 C/W with adequate thermal vias, expect approximately 50 C junction temperature rise above ambient. Use the published theta-JC value and consider airflow over the top of the package for high-utilization designs.
Route high-speed transceiver channels with 100 ohm differential impedance and keep length matching within the budget specified in the Stratix II device handbook. Maintain a continuous reference ground plane beneath all transceiver lanes and avoid routing signals over plane splits. Keep configuration pins TMS, TCK, TDO, TDI, and nCONFIG clean by routing them away from noisy nets. Decouple each PLL power pin with a 0.1 uF and 0.001 uF pair as close to the ball as possible.
Do not leave any Stratix II user I/O floating - tie unused I/O pins to a defined logic level per the device handbook or set them as input tri-stated with weak pull-up in the Quartus II pin assignment editor. Verify JTAG chain order matches the physical board layout, otherwise configuration will fail silently. Plan configuration mode (AS, PS, JTAG) early in the design; mixing modes after layout can require board rework because mode-select pins have specific pull-up/pull-down requirements.
Compliance Information
RoHS, REACH, and conflict-minerals compliance not stated in the provided web data. Lead-free confirmed by the 'N' suffix in the MPN per Altera ordering convention. AEC-Q100 not applicable to FPGAs.
