EP2S90F1020C5N - Stratix II FPGA, 90K LE, 758 I/O, 1020-BGA | Intel
MPN: EP2S90F1020C5N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1850 | $1,850.00 |
| 10 | $1725 | $17,250.00 |
| 100 | $1560 | $156,000.00 |
| 500 | $1395 | $697,500.00 |
| 1,000 | $1240 | $1,240,000.00 |
EP2S90F1020C5N Overview
An FPGA (Field Programmable Gate Array) is a reprogrammable digital logic device that sits between simple CPLDs and fixed-function ASICs in the design complexity hierarchy: programmable logic -> FPGA -> structured ASIC -> full-custom ASIC. The Stratix II family was Altera's second-generation high-performance architecture, adding adaptive logic modules (ALMs), on-chip transceivers in select variants, and dedicated DSP blocks for high-throughput arithmetic, making it well suited for ASIC prototyping, DSP pipelines, and high-speed parallel I/O.
Key features include 12 dedicated 18x18 multipliers and multiple embedded DSP blocks for fixed- and floating-point arithmetic, 4,520,488 bits of TriMatrix embedded SRAM distributed across M512/M4K/M-RAM blocks, 758 user I/Os supporting multiple I/O standards, and the Altera (now Intel) Quartus II design flow for synthesis, place-and-route, and timing closure. The -5 speed grade places the part in the upper performance bin for the family, at the cost of higher dynamic power than the -C4 or -C3 grades.
Typical applications include ASIC prototyping and emulation platforms, high-speed digital signal processing, telecommunications line cards, video and image processing pipelines, and military/aerospace signal-processing boards. The 1020-ball FBGA exposes enough user I/O to support multiple parallel external memory interfaces (DDR/DDR2/QDRII) and multi-gigabit transceiver channels via companion PHY devices.
When designing with this device, plan for a multi-layer PCB with continuous power planes, low-impedance decoupling on every VCC/GND pair, and a heatsink or forced airflow over the FBGA because the 90 nm Stratix II family dissipates significant dynamic power at high toggle rates. Use the Quartus II PowerPlay analyzer with realistic toggle-rate vectors to estimate junction temperature before sign-off.
This page synthesizes distributor availability, Stratix II family alternatives from the Site MPN list, and practical design notes that go beyond what the manufacturer datasheet alone provides.
Drop-in alternatives for EP2S90F1020C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1020C5N (same form factor and footprint) β differing in Package, Operating Temperature, Speed Grade, Embedded DSP Blocks, Mounting Type.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S90F1020C4N
β Drop-Inβ In Stock
$1320 / Unit
View Datasheet βEP2S90F1020C3N
β Drop-Inβ In Stock
$1995 / Unit
View Datasheet βEP2S90F1020C5
β Drop-Inβ In Stock
$1450 / Unit
View Datasheet βEP2S90F1020C4
β Drop-Inβ In Stock
$1325 / Unit
View Datasheet βEP2S90F1020C3
β Drop-Inβ In Stock
$640 / Unit
View Datasheet βEP2S130F1020C5N
β Drop-Inβ In Stock
$1320 / Unit
View Datasheet βEP2S90F1020C5N Maximum Ratings & Electrical Characteristics
| Series | Stratix II |
| Family | Stratix II (EP2S90) |
| Process Node | 90 nm |
| Logic Elements (LEs) | 90,960 |
| Embedded Memory (TriMatrix) | 4,520,488 bits |
| Embedded Multipliers (18x18) | 12 (DSP blocks) |
| User I/Os | 758 |
| Maximum User I/O Pins | 758 |
| Package | 1020-ball FBGA (FineLine BGA) |
| Speed Grade | -5 (commercial, faster bin) |
| Operating Temperature | 0C to +85C (commercial) |
| Lead-Free / RoHS | Lead Free / RoHS Compliant |
| Mounting Type | Surface Mount (BGA) |
| Design Tool | Quartus II (legacy, Altera) |
EP2S90F1020C5N 1020-ball fbga (fineline bga) Pin Configuration Guide
Pin configuration for EP2S90F1020C5N (1020-ball fbga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1020C5N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1020C5N is suitable for 6 applications: ASIC Prototyping and Emulation, High-Speed DSP Pipelines, Telecommunications Line Cards, Video and Image Processing, Military and Aerospace Signal Processing, Industrial Control and Test Equipment.
ASIC Prototyping and Emulation
The EP2S90F1020C5N's 90,960 logic elements and 4,520,488 bits of embedded memory make it a strong fit for ASIC prototyping and in-circuit emulation of mid-complexity ASICs. Designers map RTL into the Stratix II ALMs, use the -5 speed grade to hit emulated clock frequencies above 200 MHz, and partition large ASICs across multiple FPGAs using the 758 user I/Os as inter-FPGA channels. The TriMatrix memory (M512, M4K, M-RAM blocks) emulates on-chip SRAMs and FIFOs that closely mirror the timing of the target ASIC. Compared with ASIC tape-out, an FPGA prototype reduces bring-up time from months to weeks.
Recommended
High-Speed DSP Pipelines
The Stratix II DSP blocks in the EP2S90F1020C5N deliver dedicated 18x18 multipliers and adder/accumulator chains, enabling fixed- and floating-point DSP pipelines for radar, software-defined radio, and video processing. In the -5 speed grade, DSP blocks sustain clock rates above 250 MHz, which is sufficient for multi-tap FIR filters, FFT butterflies, and matrix-multiply accelerators. The 12 dedicated multipliers per DSP block and the wide embedded memory bandwidth let designers keep data on-chip, avoiding the bottleneck of external DDR accesses. The 758 I/Os support multiple parallel data ports at LVDS or HSTL signaling.
Recommended
Telecommunications Line Cards
The EP2S90F1020C5N's combination of 758 user I/Os, embedded transceivers in companion Stratix II variants, and on-chip TriMatrix memory suits it for telecommunications line-card designs where multiple channels of packet processing, framing, and traffic management must run in parallel. The -5 speed grade handles 10 Gbps auxiliary logic and OC-48 / STM-16 class fabric interfaces. Designers pair it with external PHY devices for SERDES, since the EP2S90F1020C5N in this 1020-ball package provides LVDS and HSTL I/O rather than hardened transceivers. The high I/O count also supports glueless connection to QDRII and DDR2 external memories for packet buffering.
Recommended
Video and Image Processing
Video pipelines benefit from the EP2S90F1020C5N's wide embedded memory bandwidth and parallel DSP blocks. Designers implement motion estimation, deinterlacing, scaling, and color-space conversion directly in the ALMs and DSP slices, keeping intermediate frame buffers on-chip to avoid external DRAM round-trips. The 758 user I/Os accept multiple parallel video ports (BT.1120, BT.656, or LVDS-based DisplayPort/HDMI bridges), and the -5 speed grade sustains pixel clocks above 150 MHz for 1080p60 processing. Quartus II's Video and Image Processing Suite (VIPSU) provides ready-made IP for common kernels.
Recommended
Military and Aerospace Signal Processing
Long-life-cycle programs in military and aerospace continue to specify the EP2S90F1020C5N because of its mature Quartus II tool flow, documented pinout, and the availability of ruggedized screened variants from component brokers. The part's -5 speed grade supports the high-throughput signal-processing chains required in radar, electronic warfare, and satellite payload subsystems. Designers must perform their own up-screening and counterfeit-detection steps when sourcing from brokers, since the original Altera military-grade flow for Stratix II has been wound down. The 1020-ball FBGA accommodates the dense routing needed for multi-channel ADC/DAC interfaces.
Recommended
Industrial Control and Test Equipment
The EP2S90F1020C5N is used in high-end industrial test equipment (ATE, protocol analyzers, oscilloscopes) where its 758 I/Os allow direct connection to many parallel test points without external muxes. The on-chip DSP blocks accelerate FFT-based spectrum analysis and digital filtering in real time. Designers use the Quartus II SOPC Builder to embed Nios II soft processors for housekeeping tasks alongside custom DSP hardware. The commercial 0C to +85C temperature range covers most factory-floor enclosures, while the -5 speed grade sustains the high sample rates required for modern serial-bus protocol analyzers.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1020C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1020C4N | EP2S90F1020C3N | EP2S90F1020C5 | EP2S90F1020C4 | EP2S130F1020C5N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 1020-ball FBGA | 1020-ball FBGA (same) | 1020-ball FBGA (same) | 1020-ball FBGA (same) | 1020-ball FBGA (same) | 1020-ball FBGA (same) |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 132,540 |
| Embedded Memory (bits) | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 6,747,840 |
| Speed Grade | -5 (fastest) | -4 | -3 | -5 | -4 | -5 |
| Temperature Range | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Process Node | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm | 90 nm |
Key Differentiators
- Fastest speed grade in the EP2S90F1020 family (vs EP2S90F1020C4N)
- Smaller die than EP2S130 in same 1020-ball FBGA (vs EP2S130F1020C5N)
- Larger 1020-ball BGA exposes 758 user I/Os (vs EP2S90F780C4N)
Design Notes
The EP2S90F1020C5N in a 1020-ball FBGA can dissipate 5-10 W in real designs with high toggle rates. Use Quartus II PowerPlay early in the design cycle with realistic toggle rates to estimate junction temperature. Plan for at least 4-layer PCB with continuous inner ground/power planes, and either a heatsink with thermal interface material or 200-400 LFM forced airflow over the BGA. Estimated: at 8 W dissipation with theta_JA around 12 C/W (still-air, JEDEC test board), junction temperature would rise 96 C above ambient, so airflow is essential for any design above 4 W.
Decoupling is critical on Stratix II FPGAs. Use one 0.1 uF X7R 0402/0603 capacitor per VCC/VCCINT/VCCPD pair as close to the balls as the BGA escape routing allows, plus 4.7 uF and 22 uF bulk capacitors distributed across the power planes. Place PLL supply filters (ferrite bead + 10 uF + 0.1 uF) within 50 mils of the PLL analog supply pins. Use microvia-in-pad if your fab supports it, otherwise dog-bone fan-out with vias in-pad where manufacturing rules permit.
The 758 user I/Os support LVDS, HSTL, SSTL, and LVCMOS signaling. For DDR/DDR2 external memory interfaces, follow Altera's external memory interface layout guidelines: length-match the byte groups within +/-25 mils, route differential pairs with 100 ohm differential impedance, and use fly-by VTT termination for DDR2. Run Quartus II TimeQuest timing analysis with board-level delays (use the Altera Board Trace Model or extract from your own EM simulation) to close timing across voltage and temperature corners.
Do NOT use the EP2S90F1020C5N in new designs - it is NRND as of 2026-09-09 and the Quartus II tool flow is in legacy maintenance mode. For new ASIC prototyping, choose Stratix V, Cyclone V, or newer families supported by Quartus Prime Standard/Pro. If you must maintain a legacy EP2S90 design, pin your Quartus II version (do not auto-update) and verify each compiler release against your bitstream for regressions before releasing product.
Compliance Information
RoHS compliant and lead-free per Altera/Intel product page and DigiKey listing. AEC-Q100 is not applicable (FPGAs are not automotive-qualified discrete semiconductors in the AEC-Q100 sense). Halogen-free status not stated in the verified web data. The part is NRND; verify any specific compliance requirement against the manufacturer's latest PCN before procurement.
