EP2S90F1020I4 - Stratix II FPGA 90K LE 1020-FBGA | Intel
MPN: EP2S90F1020I4 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3500 | $3,500.00 |
| 10 | $3200 | $32,000.00 |
| 100 | $2850 | $285,000.00 |
| 500 | $2500 | $1,250,000.00 |
| 1,000 | $2200 | $2,200,000.00 |
EP2S90F1020I4 Overview
An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows designers to configure digital logic blocks and interconnect routing after manufacturing using a hardware description language such as Verilog or VHDL. FPGAs sit in the broader taxonomy of programmable logic -> PLD -> digital IC -> semiconductor, and are widely used for parallel DSP, high-speed serial interfaces, and prototype ASIC development where NRE costs are not yet amortized.
Key features include 12 dedicated 18x18 multipliers, 384 (9-bit) ALMs, multi-gigabit transceivers supporting up to 6.375 Gbps, and a hierarchical clock network with up to 16 global clocks. The 'I4' suffix denotes the industrial temperature grade (-40C to +100C junction), while the 'F1020' denotes the 1020-ball FBGA package. The device supports multiple I/O standards including LVDS, LVPECL, HSTL, SSTL, and PCI/PCI-X, and is supported by the Quartus II design toolchain.
Typical applications include high-performance DSP for radar and baseband processing, high-speed serial protocol bridging (PCIe, Serial RapidIO, Gigabit Ethernet), ASIC prototyping, and telecom infrastructure. Industrial -40C to +100C operating range also makes it suitable for harsh-environment embedded computing.
When designing with this device, ensure proper power sequencing of VCCINT (1.2V core) and VCCIO banks, and provide adequate thermal relief via the exposed die pad. Use the Quartus II SignalTap logic analyzer for in-system debug and verify all transceiver reference-clock routing meets the jitter mask.
This page synthesizes distributor pricing, drop-in alternatives from the Site MPN list, and practical design notes not found in the manufacturer datasheet, providing an engineering-grade reference for sourcing and selection decisions.
Drop-in alternatives for EP2S90F1020I4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1020I4 (same form factor and footprint) — differing in Package, Mounting Type, Operating Temperature, Speed Grade, Process Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90F1020I4N
✅ Drop-In✓ In Stock
$1995 / Unit
View Datasheet →EP2S90F1020C5N
✅ Drop-In✓ In Stock
$1240 / Unit
View Datasheet →EP2S90F1020C5
✅ Drop-In✓ In Stock
$1450 / Unit
View Datasheet →EP2S90F1020C4N
✅ Drop-In✓ In Stock
$1320 / Unit
View Datasheet →EP2S90F1020C4
✅ Drop-In✓ In Stock
$1325 / Unit
View Datasheet →EP2S130F1020I4
✅ Drop-In✓ In Stock
$1395 / Unit
View Datasheet →EP2S90F1020I4 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements (LE) | 90,960 |
| Equivalent LEs (with ALM) | up to 180,000 |
| Embedded Memory (bits) | 4,520,488 |
| Total RAM Blocks | 758 (M512/M4K/M-RAM) |
| DSP Blocks (18x18 multipliers) | 12 |
| Maximum User I/O | 758 |
| Transceivers | Up to 12 (6.375 Gbps) |
| Process Technology | 90 nm all-layer copper SRAM, 1.2 V core |
| Package | 1020-ball FBGA (33x33 mm) |
| Operating Temperature | -40C to +100C (industrial, I4 grade) |
| Supply Voltage (VCCINT) | 1.2 V |
| Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Mounting Type | Surface Mount (SMD/SMT) |
| MSL Level | 3 |
| Lead-Free / RoHS | Compliant |
EP2S90F1020I4 1020-ball fbga (33x33 mm) Pin Configuration Guide
Pin configuration for EP2S90F1020I4 (1020-ball fbga (33x33 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1020I4.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1020I4 is suitable for 7 applications: High-Performance DSP for Radar and Baseband, High-Speed Serial Protocol Bridging, ASIC Prototyping and Emulation, Telecom Infrastructure Line Cards, Industrial Control and Machine Automation, Medical Imaging and Diagnostics, Test & Measurement Instrumentation.
High-Performance DSP for Radar and Baseband
The EP2S90F1020I4's 90,960 logic elements and 12 dedicated 18x18 multipliers make it ideal for digital signal processing applications such as radar pulse compression, baseband channelization, and software-defined radio (SDR) front-ends. The 4.5 Mbits of embedded memory provides low-latency buffer storage for FFT windows, reducing dependency on external SRAM and enabling sustained throughput above 100 GMACs. The multi-gigabit transceivers route digitized RF samples to DSP pipelines at up to 6.375 Gbps, supporting wideband capture. Industrial temperature grade (-40C to +100C) ensures operation in outdoor telecom and defense deployments where ambient temperatures vary widely.
Recommended
High-Speed Serial Protocol Bridging
The EP2S90F1020I4 integrates up to 12 multi-gigabit transceivers supporting PCIe Gen1/Gen2, Serial RapidIO, Gigabit Ethernet, and XAUI in a single device. Designers can implement multi-protocol bridge chips that aggregate serial lanes from line cards and fan out to backplane or switch fabrics. The 758 user I/Os allow direct connection to DDR/DDR2 memory controllers and parallel peripheral buses alongside the serial interfaces, simplifying board layout. The ALM structure provides deterministic timing closure at 6.375 Gbps, critical for protocol compliance testing.
Recommended
ASIC Prototyping and Emulation
With up to 180,000 equivalent LEs, the EP2S90F1020I4 can emulate complex ASIC designs before tape-out, including multi-core SoCs, custom processor pipelines, and accelerator fabrics. Designers partition the ASIC RTL across multiple Stratix II FPGAs using the Quartus II multi-FPGA partitioning flow, with the 758 I/Os per device providing the interconnect bandwidth needed between FPGA partitions. The 4.5 Mbits of embedded memory maps efficiently to register files and on-chip buffers. Industrial temperature grade supports in-vehicle and aerospace ASIC prototyping where lab temperature chambers replicate operating conditions.
Recommended
Telecom Infrastructure Line Cards
The EP2S90F1020I4 supports telecom line-card functions such as packet classification, traffic shaping, and OTN (Optical Transport Network) framer/mapper implementation. Its 758 user I/Os interface to multiple SFP+/XFP optical modules via LVDS, while the embedded transceivers handle 10G Ethernet and OC-192 framer connections directly. The ALM-based architecture delivers deterministic latency critical for OTN jitter compliance, and the 4.5 Mbits of embedded memory buffers packets during QoS scheduling. Industrial temperature grade suits outdoor remote radio heads and central-office deployments.
Recommended
Industrial Control and Machine Automation
The EP2S90F1020I4 is well-suited for industrial PLC, motion controller, and machine vision applications that demand deterministic real-time processing combined with high I/O count. The 758 user I/Os interface directly to motor encoder inputs, sensor arrays, and high-speed camera links via LVDS, while the 12 DSP blocks perform PID loop closure and FFT-based vibration analysis in real time. Industrial -40C to +100C temperature operation ensures reliable deployment in factory-floor enclosures, and the 1.2V core supply simplifies thermal management in sealed IP67 housings.
Recommended
Medical Imaging and Diagnostics
The EP2S90F1020I4 supports real-time medical imaging modalities such as ultrasound beamforming, CT reconstruction back-projection, and MRI gradient control. Its 12 dedicated 18x18 multipliers and 4.5 Mbits embedded memory accelerate FIR filter chains and FFT-based image reconstruction algorithms with deterministic latency. The 758 user I/Os accept raw data from high-channel-count ADC arrays, while multi-gigabit transceivers stream processed images to display controllers. Industrial temperature grade ensures reliable operation in clinical environments, though medical safety certification (IEC 60601) must be validated at the system level.
Recommended
Test & Measurement Instrumentation
The EP2S90F1020I4 serves as the central processing engine in high-end oscilloscopes, logic analyzers, and protocol analyzers, where its 90K LEs implement deep acquisition memory control, real-time trigger logic, and protocol decoding. The 6.375 Gbps transceivers capture and process high-speed serial data streams, while the 758 user I/Os drive display controllers and front-panel interfaces. Industrial temperature grade supports portable field-instrument use cases. Designers pair the FPGA with high-speed ADCs and DACs, leveraging the embedded memory for deep sample buffer storage.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1020I4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1020I4N | EP2S90F1020C5N | EP2S90F1020C5 | EP2S90F1020C4N | EP2S90F1020C4 | EP2S130F1020I4 |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1020-FBGA (33x33 mm) | 1020-FBGA (33x33 mm) - same | 1020-FBGA (33x33 mm) - same | 1020-FBGA (33x33 mm) - same | 1020-FBGA (33x33 mm) - same | 1020-FBGA (33x33 mm) - same | 1020-FBGA (33x33 mm) - same |
| Logic Elements (LE) | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 130,060 (+43%) |
| Embedded Memory (bits) | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 6,747,840 (+49%) |
| DSP Blocks (18x18 mult) | 12 | 12 | 12 | 12 | 12 | 12 | 16 (+33%) |
| Maximum User I/O | 758 | 758 | 758 | 758 | 758 | 758 | 742 (-2%) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Speed Grade | I4 | I4 | C5 (faster) | C5 (faster) | C4 (slower ~15%) | C4 (solder ~15%) | I4 |
| Lead-Free Finish | Yes (Pb-free implied for I4) | Yes (N suffix explicit) | Yes (N suffix explicit) | No (with lead) | Yes (N suffix explicit) | No (with lead) | No (with lead implied) |
Key Differentiators
- Higher logic density in same 1020-FBGA footprint compared to EP2S60 variants (vs EP2S60F1020I4N)
- Industrial temperature grade with same logic capacity vs commercial variants (vs EP2S90F1020C5N)
- Faster I4 speed grade vs C4 in same package (vs EP2S90F1020C4N)
Design Notes
The EP2S90F1020I4 requires a 1.2V core supply (VCCINT) and bank-specific VCCIO supplies (1.5V/1.8V/2.5V/3.3V). Use a multi-rail sequencing controller such as the LTC2935 or TPS54xx family to enforce VCCINT-before-VCCIO power-up, preventing internal I/O latch-up. Decoupling: place 0.1uF X7R 0402/0201 capacitors within 2 mm of every VCC pin and at least one 470uF bulk capacitor near the device. Transceiver analog supplies (VCCA, VCCP, VCCR) require ferrite-bead isolation from digital VCCINT to minimize coupled jitter.
The 1020-FBGA package exposes the die through a center thermal pad for board-level heat spreading. Estimated: at 1.0W internal dissipation (typical for ~70% utilization), a 4-layer PCB with 1 oz copper on outer layers and 0.5 oz on inner layers yields theta_JA of approximately 12-15 C/W, allowing operation up to ~85C ambient without a heatsink. For full industrial -40C to +100C operation, recommend thermal vias (0.3 mm pitch, 0.2 mm drill) under the center pad connecting to an inner copper pour. At sustained junction temperature above 100C, the device derates Fmax by ~5% per 10C rise.
The 1020-ball FBGA uses 1.00 mm ball pitch; route signals on the top layer using 0.10 mm (4 mil) traces with 0.15 mm spaces between BGA escape vias. Use microvia or via-in-pad technology for inner-row BGA balls to escape from the dense center array. Maintain 100-ohm differential impedance for transceiver pairs (typically 4-mil/8-mil/4-mil stackup) and 50-ohm single-ended for general-purpose I/O. Length-match clock-to-PLL reference-clock traces within 0.5 mm (5 ps) and verify signal integrity with 3D EM simulation at the transceiver rates.
Do not connect VCCIO banks to incompatible voltage standards - mixing 3.3V and 1.5V on adjacent banks without proper isolation corrupts configuration. Always issue a full configuration reload after JTAG-driven register changes, otherwise state machines may enter undefined states. When migrating from EP2S60 to EP2S90 in the same 1020-FBGA, verify that any hard IP blocks (transceivers, memory controllers) reference the correct device library - Quartus II Quartus Fitter errors are common if the wrong device ID is selected.
Compliance Information
RoHS compliance confirmed via Intel product page. I4 suffix indicates industrial temperature grade per Altera/Intel naming convention. AEC-Q100 qualification not applicable for FPGA logic devices. REACH and conflict-mineral status not explicitly stated in provided data; refer to Intel Product Content Declarations for confirmation.
