EP2S90H484C5 - 90K LE Stratix II FPGA, 484-BGA | Intel / Altera
MPN: EP2S90H484C5 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
EP2S90H484C5 Overview
What is an FPGA? A Field-Programmable Gate Array is a semiconductor integrated circuit whose logic functionality is defined by the user after manufacturing rather than at the fab. FPGAs occupy the category hierarchy: programmable logic -> logic IC -> integrated circuit -> semiconductor. The Stratix II family specifically targets high-performance signal processing and ASIC prototyping, combining embedded multipliers, TriMatrix memory blocks, and high-speed transceivers in a single device.
Key features of the EP2S90H484C5 include 4,548 LABs (Logic Array Blocks), 12 embedded DSP blocks for hardware multiplication, dedicated external memory interfaces supporting DDR/DDR2/QDRII SRAM, and up to 12 high-speed transceiver channels. The device supports configuration via passive serial, JTAG, and Altera-enhanced configuration modes, with built-in error detection and correction (EDC) for configuration RAM.
Technically, the EP2S90H484C5 implements an adaptive logic module (ALM) architecture that achieves approximately 2.5x the logic capacity of previous-generation Stratix devices at the same silicon area. The fine-grained ALM combines look-up tables, adders, and registers in 8-bit groupings, optimizing for both register-rich and arithmetic-intensive designs.
Typical applications include high-performance ASIC prototyping, wireless baseband signal processing, high-definition video processing, military radar and sonar systems, and test & measurement equipment. The 484-ball FCBGA package supports high I/O count designs requiring numerous LVDS, DDR memory interfaces, and parallel processing buses.
Designers should pay attention to power distribution network design on the FCBGA - the 1.2V core requires substantial decoupling (typically 100uF bulk plus per-pin 0.1uF/1nF ceramics) and proper power sequencing to prevent inrush damage. Thermal management is critical: at full utilization the device can dissipate 10-15W, requiring thermal vias under the package and forced-air cooling in most deployments.
This page synthesizes distributor pricing, drop-in alternative listings, and practical design notes not found in the manufacturer datasheet alone, enabling faster BOM decisions and design-in for engineers working on Stratix II based systems.
Drop-in alternatives for EP2S90H484C5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90H484C5 (same form factor and footprint) β differing in DSP Blocks, Operating Temperature, Package, Mounting Type, Process Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S90H484C4
β Drop-Inβ In Stock
$2476.87 / Unit
View Datasheet βEP2S90H484C4N
β Drop-Inβ In Stock
$215 / Unit
View Datasheet βEP2S90F484C5
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484C4N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484C3N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90H484C5 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 90,960 |
| Embedded Memory Bits | 4,520,488 |
| User I/Os | 308 |
| LABs (Logic Array Blocks) | 4,548 |
| Package | 484-Ball FC-HFBGA (Flip-Chip BGA) |
| Process Technology | 90 nm |
| Core Supply Voltage | 1.2 V |
| Maximum Internal Clock Frequency | 609.76 MHz |
| DSP Blocks | 12 embedded multiplier blocks |
| Configuration Method | Passive Serial, JTAG, Fast Passive Parallel |
| Mounting Type | Surface Mount |
| Operating Temperature | Commercial (0C to +85C) - 'C' speed grade |
| Speed Grade | 5 (Commercial) |
EP2S90H484C5 484-ball fc-hfbga (flip-chip bga) Pin Configuration Guide
Pin configuration for EP2S90H484C5 (484-ball fc-hfbga (flip-chip bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90H484C5.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90H484C5 is suitable for 6 applications: ASIC Prototyping, Wireless Baseband Signal Processing, High-Definition Video Processing, Military Radar and Sonar Systems, Test & Measurement Equipment, High-Speed Serial Connectivity Bridge.
ASIC Prototyping
The EP2S90H484C5 is well-suited for ASIC prototyping because its 90,960 logic elements and 4,520,488 bits of embedded memory can map complex ASIC netlists at 1:1. The 90nm Stratix II architecture delivers up to 609.76 MHz internal Fmax, enabling designers to validate timing on representative gate-level designs before committing to silicon. The 484-ball FC-HFBGA provides 308 user I/Os, sufficient for ASIC-class peripheral buses and boundary-scan chains. Using the device with Quartus II and the SOPC Builder allows RTL design iteration cycles measured in hours rather than weeks, dramatically reducing time-to-prototype for gate-rich ASICs.
Recommended
Wireless Baseband Signal Processing
The EP2S90H484C5's 12 dedicated DSP blocks enable parallel multiply-accumulate operations ideal for wireless baseband algorithms including FFT, channel coding, and digital up/down conversion. Combined with 4.5 Mbits of embedded memory, the device can buffer symbol data on-chip to eliminate external memory accesses in real-time baseband paths. The 484-ball FC-HFBGA's 308 I/Os support multiple antenna interfaces and CPRI/OBSAI backhaul links. Designers targeting 3G/4G baseband processing benefit from the ALM architecture's efficient mapping of arithmetic-heavy DSP functions.
Recommended
High-Definition Video Processing
High-definition video pipelines require massive parallel datapaths for pixel processing, color-space conversion, and motion estimation - exactly the workload profile that fits the EP2S90H484C5's 90,960-LE fabric. The 4,520,488-bit TriMatrix memory provides line buffers and frame-storage capability without external SRAM, and the 308 user I/Os accommodate multiple BT.656 / BT.1120 / DVI / HDMI input channels simultaneously. At 609.76 MHz internal Fmax, the device can process 1080p60 video streams at full pixel clock rates with margin. Designers building broadcast-grade processing equipment use Stratix II for its deterministic latency and DSP-rich fabric.
Recommended
Military Radar and Sonar Systems
The EP2S90H484C5 suits military radar and sonar processing due to its deterministic latency, high DSP throughput, and ability to run multiple matched-filter and FFT operations in parallel. The 12 DSP blocks deliver parallel 18x18 multiplies required for pulse-Doppler radar processing, while 4.5 Mbits of embedded memory supports range-bin buffering. The 484-ball FC-HFBGA package's commercial temperature rating makes it appropriate for ruggedized indoor electronics bays; ruggedized deployments would use the industrial-grade EP2S90F484I4 variant family instead. Long-term support concerns for military programs make Intel's NRND status a key risk factor for new programs.
Recommended
Test & Measurement Equipment
Automated test equipment, logic analyzers, and protocol exercisers benefit from the EP2S90H484C5's high I/O count (308 pins) and protocol-flexible I/O banks supporting LVDS, LVCMOS, and HSTL simultaneously. Designers can implement protocol-specific stimulus generators, bit-error-rate testers, and pattern-matching receivers entirely in the FPGA fabric. The 90nm process and 1.2V core keep power consumption manageable despite 90K logic elements, and Quartus II's SignalTap embedded logic analyzer provides on-chip debug visibility for T&M applications. Replacement of obsolete custom ASICs in legacy test platforms is a common Stratix II deployment scenario.
Recommended
High-Speed Serial Connectivity Bridge
Stratix II devices with embedded transceivers - the 'GX' variants - support multi-gigabit serial links, but the EP2S90H484C5 (non-GX) still serves as a parallel bridge/aggregator between high-speed serial ports and legacy parallel buses. The 308 user I/Os accommodate wide parallel data paths, while the 90,960 logic elements can implement protocol conversion, data framing, and rate-matching FIFOs. Telecom equipment manufacturers have long used Stratix II for protocol-bridging applications between legacy TDM buses and newer packet-based fabrics. The 484-FCBGA's signal integrity supports multi-hundred-MHz parallel interfaces with proper PCB stackup.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90H484C5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90H484C4 | EP2S90H484C4N | EP2S90F484C5 | EP2S90F484C5N | EP2S90F484C4N | EP2S90F484C3N |
|---|---|---|---|---|---|---|---|
| Brand | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Package | 484-Ball FC-HFBGA | 484-Ball FC-HFBGA - same | 484-Ball FC-HFBGA - same | 484-Ball FineLine BGA - same ball count | 484-Ball FineLine BGA - same ball count | 484-Ball FineLine BGA - same ball count | 484-Ball FineLine BGA - same ball count |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Embedded Memory Bits | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 |
| User I/Os | 308 | 308 | 308 | 308 | 308 | 308 | 308 |
| Core Supply Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
| Speed Grade | C5 (fastest) | C4 (slower) | C4 (slower) | C5 (same as target) | C5 (same as target) | C4 (slower) | C3 (slowest) |
| Operating Temperature | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Same 90K-LE Stratix II die with only speed-grade downgrade (vs EP2S90H484C4 / EP2S90H484C4N)
- F484 FineLine BGA package variant with same LE count (vs EP2S90F484C5 / EP2S90F484C5N / EP2S90F484C4N)
- Slowest C3 grade option for budget/availability (vs EP2S90F484C3N)
Design Notes
Estimated: At 90% utilization the EP2S90H484C5 can draw 10-15W on the 1.2V core rail; budget a switching regulator with at least 20W capacity. Use a minimum of 100uF bulk polymer-tantalum decoupling on VCCINT plus per-pin 0.1uF X7R ceramic and 1nF NP0 ceramic to handle 90nm core transient spikes. Power-on sequence per Altera datasheet: VCCINT first, then VCCPD, then VCCIO banks - violating this sequence can damage the device.
The 484-ball FC-HFBGA has a JEDEC-standard thermal resistance theta-JA around 11-14 C/W with proper thermal vias under the BGA. Estimated: at 12W dissipation and 11 C/W theta-JA the junction-to-ambient temperature rise is 132C, exceeding the 85C commercial rating - a heatsink with thermal interface material or forced-air cooling (>=200 LFM) is required for full utilization. Place thermal vias in a 4x4 array directly under the package center per Altera Stratix II Hardware Reference Design guidelines.
Use a minimum 8-layer PCB stackup for the 484-ball FC-HFBGA with dedicated ground and power planes. Differential pair routing (LVDS) should maintain 100 ohm differential impedance with matched trace lengths within 50 mils. DDR/DDR2 memory interfaces on Stratix II require strict length matching (data within +/-25 mils of strobe) and proper termination - reference Altera's External Memory Interface Handbook for the specific controller used.
Three common Stratix II mistakes to avoid: (1) Do not use older Quartus II versions (<7.2) with EP2S90H484C5 - some configuration bugs affect large Stratix II devices; (2) Do not omit the configuration flash memory EPCS16/EPCS64 - volatile SRAM requires configuration at every power-on; (3) Do not ignore MSL (Moisture Sensitivity Level) on the FC-HFBGA package - the device is MSL3 or MSL4 and requires dry-pack storage and pre-bake if exposure exceeds floor life.
Place the JTAG header (Altera USB-Blaster pinout) on a board-edge accessible location for programming and debug. Keep high-speed transceiver routes (if used) on the top layer only, with GND stitching vias every 1/4 wavelength. The CLK inputs are pin-limited on the 484-FCBGA; place the primary clock oscillator within 1 inch of the assigned clock pin and use microstrip routing with controlled impedance.
Compliance Information
RoHS / lead-free / halogen-free status was not explicitly confirmed in the retrieved web data for EP2S90H484C5 as of 2026-09-09. The N-suffixed variants (EP2S90H484C4N, EP2S90F484C5N, EP2S90F484C4N, EP2S90F484C3N) are typically lead-free per Altera's lead-free part numbering convention, but the non-N variants (including EP2S90H484C5) require manufacturer lot-level confirmation. AEC-Q100 not applicable - this is an FPGA not an automotive IC. Reach and conflict-minerals status require manufacturer material declaration request.
