EP2S90H484C4 - Stratix II FPGA, 90K LE, 484-FCBGA | Intel
MPN: EP2S90H484C4 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4128.12 | $4,128.12 |
| 10 | $3715.31 | $37,153.10 |
| 100 | $3302.5 | $330,250.00 |
| 500 | $2889.69 | $1,444,845.00 |
| 1,000 | $2476.87 | $2,476,870.00 |
EP2S90H484C4 Overview
A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs/ALMs), programmable interconnect, and dedicated hard IP such as transceivers, memory, multipliers, and PLLs. FPGAs sit in the broader taxonomy of programmable logic devices (PLD) -> logic IC -> integrated circuit -> semiconductor, and offer ASIC-like density with the time-to-market advantage of in-system reprogrammability.
Key features of the EP2S90H484C4 include twelve global clock networks, twelve PLLs for high-frequency clock synthesis, dedicated DSP blocks for high-throughput multiplication, and support for external memory interfaces including DDR, DDR2, QDR, QDRII, and RLDRAM. The 308 I/Os support multiple I/O standards (LVDS, SSTL, HSTL, LVCMOS, LVTTL, PCI-X), enabling direct interfacing with memories, backplanes, and parallel ASIC/ASSP buses without external level translation.
Stratix II architecture uses an adaptive logic module (ALM) as its fundamental building block, allowing the device to pack combinatorial and sequential logic more efficiently than the 4-input LUT-based architectures of its predecessors. Combined with dedicated on-chip multipliers and TriMatrix memory (M512/M4K/M-RAM), the EP2S90H484C4 is optimized for high-performance DSP, telecom baseband, and high-speed datapath designs that require parallel arithmetic pipelines.
Typical applications include high-performance digital signal processing (DSP) for wireless base stations, telecom switching fabric, video and imaging processing pipelines, high-speed serial protocol bridging, ASIC prototyping, and military/aerospace signal processing platforms. The wide I/O count also suits parallel data-acquisition front ends and high-bandwidth packet processing engines.
When designing with the EP2S90H484C4, plan a multi-layer PCB with dedicated power and ground planes, controlled-impedance routing for DDR2 memory interfaces, and matched-length clock traces. Decoupling must follow the Stratix II handbook reference design, with multiple bulk and high-frequency capacitors placed close to the package balls. Configuration can be loaded via JTAG, passive serial, or via an external EPC configuration device.
This page synthesizes distributor pricing tiers, drop-in same-family alternatives with the same 484-FCBGA footprint, and design notes that complement (rather than duplicate) the manufacturer Stratix II Device Handbook.
Drop-in alternatives for EP2S90H484C4 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90H484C4 (same form factor and footprint) β differing in DSP Blocks, Operating Temperature, Package, Mounting Type, Process Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S90F484C4N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484C5N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484I4
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484I4N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484C3
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90F484C4
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP2S90H484C4 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Logic Elements | 90,960 |
| Adaptive Logic Modules (ALMs) | 36,384 |
| Logic Array Blocks (LABs) | 4,548 |
| Maximum User I/O Pins | 308 |
| Total On-Chip Memory | 4,520,488 bits |
| Process Technology | 90 nm CMOS |
| Core Supply Voltage | 1.2 V |
| Maximum Internal Clock Frequency | 711.24 MHz |
| Package | 484-ball FCBGA (HBGA), 27 x 27 mm, 1.0 mm pitch |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | 0 C to +85 C (Commercial) |
| Configuration Method | JTAG / Passive Serial / EPC configuration device |
| DSP Blocks | Yes (dedicated 18x18 multipliers) |
| PLLs | 12 |
| RoHS Status | Compliant |
EP2S90H484C4 Pin Configuration
| Pin G1 | GND β Ground |
| Pin G2 | VCCINT β Core supply (1.2 V) |
| Pin H5 | I/O Bank 1 β User I/O bank 1 |
| Pin AA22 | DIFFIO_TX_n7 β Differential transmit pair (negative) |
| Pin AB1 | VCCIO1 β I/O bank 1 reference voltage |
| Pin AE23 | PLL1_CLKOUTp β PLL1 clock output (positive) |
| Pin AF11 | DPCLK0 β DPCLK clock input pin 0 |
| Pin B12 | TMS β JTAG Test Mode Select |
| Pin C23 | TCK β JTAG Test Clock |
| Pin D14 | TDI β JTAG Test Data In |
| Pin E22 | TDO β JTAG Test Data Out |
| Pin F5 | MSEL0 β Configuration mode select 0 |
| Pin G23 | MSEL1 β Configuration mode select 1 |
| Pin J12 | nCONFIG β Configuration control (active low) |
| Pin K1 | nSTATUS β Configuration status (active low) |
| Pin L23 | CONF_DONE β Configuration done indicator |
| Pin M14 | nCE β Chip enable (active low) |
| Pin N5 | nCEO β Chip enable output for daisy chain |
| Pin P22 | DATA0 β Configuration data bit 0 |
| Pin R12 | DCLK β Configuration clock input |
Typical Applications
EP2S90H484C4 is suitable for 6 applications: Wireless Baseband DSP, Telecom Switching Fabric, Video and Imaging Processing Pipeline, High-Speed ASIC Prototyping, High-Bandwidth Packet Processing Engine, Industrial High-Speed Data Acquisition Front End.
Wireless Baseband DSP
The EP2S90H484C4's 90,960 logic elements and dedicated 18x18 multipliers make it well-suited for wireless baseband digital signal processing, where parallel arithmetic pipelines handle channel filtering, equalization, and modulation. The 4,520 Kbits of TriMatrix on-chip memory minimize external memory accesses for symbol-rate processing, while 12 PLLs synthesize the multiple clock domains required by RF front-end converters and MAC interfaces. Designers typically instantiate this FPGA between ADC/DAC up/down-converters and a host processor over LVDS or HSTL links.
Recommended
Telecom Switching Fabric
With 308 user I/Os and on-chip memory of 4.52 Mbits, the EP2S90H484C4 is used in telecom switching fabrics that aggregate multiple lower-speed channels onto a higher-speed backplane. SSTL and HSTL I/O standards support direct connection to network ASICs and backplane SERDES, while the dedicated DDR/DDR2 controllers simplify buffer memory design. The commercial 0-85 C rating suits temperature-controlled central office racks.
Recommended
Video and Imaging Processing Pipeline
The EP2S90H484C4's high ALM count and DSP block density suit real-time video processing pipelines such as motion-adaptive deinterlacing, scaling, and color-space conversion. Parallelism across 36,384 ALMs enables per-pixel processing at HDTV frame rates, while the 4.52 Mbit on-chip memory supports line buffers without external SRAM. LVDS I/O accommodates direct connection to camera sensors and HDMI receivers.
Recommended
High-Speed ASIC Prototyping
Designers use the EP2S90H484C4 as a target for ASIC prototyping because its 90,960 logic elements and ample I/O provide a single-chip platform for many mid-complexity ASICs. The Quartus II design flow supports popular ASIC synthesis libraries, and the 484-FCBGA package is pin-compatible with the EP2S90F484 family variants, allowing speed-grade and temperature swaps without re-spinning the board.
Recommended
High-Bandwidth Packet Processing Engine
The EP2S90H484C4 is used in line cards where packet headers must be parsed, classified, and forwarded at wire speed. With 12 PLLs it derives the multiple clock domains required by PHY, MAC, and lookup memory, while M-RAM blocks store large flow tables. The 308 I/Os support both narrow fast links (XLAUI/SFI) via external SERDES and wide slow links to TCAM.
Recommended
Industrial High-Speed Data Acquisition Front End
The Stratix II architecture's dedicated multipliers and on-chip memory make the EP2S90H484C4 a strong fit for parallel multi-channel data-acquisition front ends in industrial test systems. With 308 I/Os and LVDS support, the device can sink simultaneous streams from multiple high-speed ADCs and perform real-time FIR filtering, FFTs, and decimation before forwarding packets upstream.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90H484C4 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F484C4N | EP2S90F484C5N | EP2S90F484I4 | EP2S90F484C3 |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | 484-FCBGA 27 x 27 mm | 484-FCBGA 27 x 27 mm - same | 484-FCBGA 27 x 27 mm - same | 484-FCBGA 27 x 27 mm - same | 484-FCBGA 27 x 27 mm - same |
| Logic Elements | 90,960 | 90,960 | 90,960 | 90,960 | 90,960 |
| Maximum User I/O | 308 | 308 | 308 | 308 | 308 |
| On-Chip Memory (bits) | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 | 4,520,488 |
| Speed Grade | C4 | C4 | C5 (faster) | I4 (industrial temp) | C3 (slower) |
| Operating Temperature | 0 C to +85 C (Commercial) | 0 C to +85 C | 0 C to +85 C | -40 C to +100 C | 0 C to +85 C |
| Process / Voltage | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Key Differentiators
- Identical 484-FCBGA footprint across all EP2S90F484 family variants (vs EP2S60F484 / EP2S130F484)
- Speed-grade options allow post-design timing optimization (vs EP2S90F484C3 (slowest grade))
- Commercial-grade cost advantage over industrial-grade option (vs EP2S90F484I4N (industrial-grade))
Design Notes
The EP2S90H484C4 requires a multi-rail supply: VCCINT (1.2 V core), VCCPD (3.3 V), and per-bank VCCIO. Use a dedicated power plane for VCCINT with bulk decoupling (220 uF minimum) and 0.1 uF/0.01 uF high-frequency capacitors placed as close as possible to each quadrant. Pre-design power estimation in the Quartus II PowerPlay tool should be performed before PCB layout to size regulators correctly.
The 484-FCBGA package at 1.0 mm pitch requires a 4-6 layer PCB stack-up with microvia (HDI) construction. Reference the Stratix II Handbook hardware section for the recommended layer stack. Matched-length differential pair routing (within 5 ps) is required for LVDS, DDR, and DDR2 interfaces; series termination must be placed within the recommended distance of the FPGA balls to maintain signal integrity.
Estimated: at 90% utilization with all DSP blocks active, the EP2S90H484C4 may dissipate 4-6 W. The 484-FCBGA package thermal resistance is approximately 8-12 C/W (theta_JB). For commercial-temperature designs, route a sufficient copper pour beneath the package balls and ensure at least 400 LFM of airflow when sustained utilization exceeds 60%. Add a heat spreader for industrial-temperature deployments.
MSEL pins must be tied to VCCPD or GND through a 1k resistor to select the correct configuration mode (JTAG, PS, AS, FPP) - a floating MSEL causes configuration failure. Do not tie CONF_DONE or nSTATUS high; both are open-drain. For JTAG chain operation, ensure that the JTAG voltage (VCCPD) matches the JTAG programmer's reference voltage, otherwise the JTAG chain will fail to enumerate.
Compliance Information
RoHS and lead-free compliant per Intel product page for Stratix II family. AEC-Q100 not applicable (FPGA, not automotive-qualified). Halogen-free status not explicitly stated in verified web data.
