EP2S90H484C4N - Stratix II FPGA 90,960 LE | Altera | BGA-484
MPN: EP2S90H484C4N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $245 | $24,500.00 |
| 250 | $230 | $57,500.00 |
| 500 | $215 | $107,500.00 |
EP2S90H484C4N Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks, routing fabric, and dedicated hard IP such as block RAM, DSP blocks, PLLs, and high-speed transceivers, all programmable after manufacture. FPGAs sit within the broader hierarchy of programmable logic devices (PLDs), bridging the gap between fixed-function ASICs and software-driven processors. They are used to implement custom parallel datapaths, hardware-accelerated algorithms, and glue logic without the NRE cost of an ASIC, making them essential in prototyping, low-volume production, and high-bandwidth signal processing.
Key features of the EP2S90H484C4N include 90,960 LEs backed by 4,548 LABs, approximately 4.5 Mbits of embedded SRAM distributed across TriMatrix memory blocks, 12 dedicated DSP blocks for fixed- and floating-point arithmetic, and 12 PLLs for clock synthesis and skew management. The H484 package exposes 308 user I/Os at a 1.0 mm ball pitch, supporting high-density board integration. The device operates from a 1.2 V core supply with separate VCCIO banks for mixed-voltage I/O standards such as LVDS, LVTTL, LVCMOS, and HSTL.
Stratix II uses a 90 nm CMOS process with a novel adaptive logic module (ALM) architecture that improves logic utilization over the previous Stratix generation. The ALM combines look-up-table and register resources in a single 8-input fracturable structure, enabling tighter packing of wide arithmetic functions. Combined with up to 12 embedded transceivers (per family datasheet) capable of multi-gigabit-per-second serial links, the EP2S90 places as a high-end DSP and protocol-bridging platform.
Typical applications include telecommunications baseband and framer designs, high-speed data acquisition, military/aerospace signal processing, ASIC prototyping, and broadcast video processing where 4.5 Mbits of block RAM and 12 DSP blocks are sized for packet buffers, FFT/iFFT pipelines, and forward-error-correction engines. The high logic capacity also suits multi-channel motor control and software-defined radio prototyping.
When designing with the EP2S90H484C4N, plan the power tree carefully: 1.2 V core current can exceed several amps under heavy DSP utilization, and the H484 flip-chip BGA requires a multi-layer PCB with continuous ground and power planes under the device for thermal dissipation. Use Altera Quartus II design software for synthesis, place-and-route, and timing closure, and follow Stratix II pin connection guidelines to leave unused I/O pins configured as inputs with weak pull-ups.
This page synthesizes distributor pricing, drop-in same-package alternatives from the Stratix II family, application guidance, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2S90H484C4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90H484C4N (same form factor and footprint) — differing in Package, Speed Grade, Operating Temperature, DSP Blocks, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S90H484C4
✅ Drop-In✓ In Stock
$2476.87 / Unit
View Datasheet →EP2S90H484C5N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP2S130F1508C3N
✅ Drop-In✓ In Stock
$270 / Unit
View Datasheet →EP2S180F1508C4N
✅ Drop-In✓ In Stock
$985 / Unit
View Datasheet →EP2S90H484C4N Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (now Intel FPGA) |
| Series | Stratix II |
| Logic Elements (LE) | 90,960 |
| LABs / CLBs | 4,548 |
| Embedded Memory (bits) | 4,520,448 (~4.5 Mbit) |
| DSP Blocks | 12 (per family datasheet) |
| PLLs | 12 (per family datasheet) |
| User I/O Count | 308 |
| Package | 484-ball FCBGA (H484), 1.0 mm pitch |
| Mounting Type | Surface Mount |
| Process Technology | 90 nm CMOS |
| Core Voltage | 1.2 V typical |
| Speed Grade | C4 (commercial, mid-speed) |
| Operating Temperature | 0C to +85C (commercial) |
| RoHS Status | Compliant |
EP2S90H484C4N 484-ball fcbga (h484), 1.0 mm pitch Pin Configuration Guide
Pin configuration for EP2S90H484C4N (484-ball fcbga (h484), 1.0 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90H484C4N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90H484C4N is suitable for 6 applications: Telecommunications Baseband Processing, High-Speed Data Acquisition Systems, ASIC Prototyping Platforms, Broadcast Video Processing, Software Defined Radio (SDR), Industrial Motion Control.
Telecommunications Baseband Processing
The EP2S90H484C4N is well suited for telecom baseband and framer designs where the 90,960 logic elements and 4.5 Mbits of TriMatrix memory deliver packet buffers, framer state machines, and protocol bridging in a single device. Its 12 DSP blocks at hundreds of MHz enable scrambling, FEC, and interleaver pipelines for SDH/SONET and OTN payloads. The 308 user I/Os support parallel backplane interfaces, while optional multi-gigabit transceivers (per Stratix II family) provide 1 Gbps to 3.125 Gbps serial links for SFI-4 or Interlaken connectivity. Compared with ASICs, the FPGA permits late-stage protocol updates critical for evolving telecom standards.
Recommended
High-Speed Data Acquisition Systems
For high-channel-count data acquisition cards, the EP2S90H484C4N's 4.5 Mbits of embedded SRAM absorb 1000s of samples at 250 MHz while the 12 dedicated DSP blocks implement FIR filtering and decimation in real time. The 308 I/Os support LVDS and DDR2 interface widths for direct connection to high-speed ADCs and DACs without external buffers. Its 90 nm Stratix II fabric can sustain 300 MHz internal clocks, sufficient for oversampling and digital down-conversion pipelines used in radar and instrumentation front-ends.
Recommended
ASIC Prototyping Platforms
ASIC prototyping requires multiple FPGAs with abundant logic and shared memory, areas where the EP2S90H484C4N excels with 90,960 LEs and 4.5 Mbits of block RAM per chip. Multi-FPGA prototyping boards partition an ASIC RTL design across two to four EP2S90 devices using HSTL or LVDS chip-to-chip links, with Quartus II's multi-device partition flow easing timing closure. The H484 FCBGA package exposes enough I/O to replicate wide on-chip buses, and the 12 DSP blocks preserve arithmetic density lost in earlier FPGA generations.
Recommended
Broadcast Video Processing
Broadcast video switchers, mixers, and transcoders rely on large pixel buffers and real-time pixel processing, both of which the EP2S90H484C4N handles through its 4.5 Mbits of embedded SRAM and 12 DSP blocks. Video pixel rates of 148.5 MHz (1080p60) and 297 MHz (3G-SDI) fit comfortably within the Stratix II fabric's 300 MHz internal clock capability. The 308 user I/Os can fan out to multiple SDI receivers, HDMI transmitters, and a downstream DSP pipeline without external logic, reducing BOM cost and board area in studio equipment.
Recommended
Software Defined Radio (SDR)
SDR prototyping platforms for tactical and commercial wireless research use the EP2S90H484C4N for digital up/down-conversion, FFT/iFFT engines, and channelization filters. Its 12 DSP blocks deliver 18x18 MAC throughput suitable for OFDM baseband at LTE sample rates, while 4.5 Mbits of embedded RAM serves as FFT working memory for 4096-point transforms. The 308 I/Os interface to dual-channel 14-bit ADCs/DACs at 250 MSPS, supporting wideband receive chains across HF, VHF, and L-band with the same hardware platform.
Recommended
Industrial Motion Control
Multi-axis CNC and robotic motion controllers use the EP2S90H484C4N to run position-loop, velocity-loop, and trajectory calculations for eight or more servo axes simultaneously. The 12 DSP blocks execute PID controllers and feed-forward compensation at 100 kHz loop rates, while 4.5 Mbits of embedded SRAM stores trajectory tables and S-curve profiles. The 308 user I/Os connect to multiple encoder channels (EnDat, BiSS, or SSI), drive enable signals, and high-speed EtherCAT or SERCOS interfaces through on-chip PLLs and LVDS transceivers, delivering deterministic control with microsecond-class latency.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90H484C4N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90H484C4 | EP2S90H484C5N | EP2S130F1508C3N | EP2S180F1508C4N |
|---|---|---|---|---|---|
| Package | 484-ball FCBGA (H484), 1.0 mm pitch | 484-ball FCBGA (H484), 1.0 mm pitch - same | 484-ball FCBGA (H484), 1.0 mm pitch - same | 1508-pin FBGA (F1508) - DIFFERENT | 1508-pin FBGA (F1508) - DIFFERENT |
| Brand | Altera (Intel FPGA) | Altera - same | Altera - same | Altera - same | Altera - same |
| Logic Elements | 90,960 | 90,960 - same | 90,960 - same | 132,540 (+45%) | 179,400 (+97%) |
| Embedded Memory (bits) | 4,520,448 | 4,520,448 - same | 4,520,448 - same | 6,747,840 | 9,383,040 |
| DSP Blocks | 12 | 12 - same | 12 - same | 16 | 24 |
| User I/O | 308 | 308 - same | 308 - same | 744 | 744 |
| Speed Grade | C4 (commercial) | C4 - same | C5 (slower) | C3 (faster) | C4 - same |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest density Stratix II member in the H484 FCBGA footprint (vs EP2S60F484C4N)
- Tray packaging variant for low-volume and prototype build flow (vs EP2S90H484C4 (tube))
- Mid-range speed grade offering balance between timing closure and cost (vs EP2S90H484C5N)
- More compact 484-ball package versus larger F1508/F1020 Stratix II devices (vs EP2S130F1508C5N)
Design Notes
Estimated: Stratix II EP2S90 devices at high toggle rates can dissipate 6-10 W from a 1.2 V core supply. The H484 FCBGA package requires a 1 oz copper power plane on every inner PCB layer to spread heat. Designers should attach a heatsink with thermal interface material if continuous FPGA junction temperature (TJ) exceeds 100C in a sealed enclosure. Recommended: use 8 layer board minimum with 4 unbroken ground/power planes directly beneath the FPGA. Critical for reliability.
Estimated: core current for a fully loaded EP2S90H484C4N can reach 4-6 amps at 1.2 V, so place at least two 22 uF bulk ceramic capacitors plus a 0.1 uF bypass within 200 mils of every VCC and GND ball pair. VCCIO banks often draw 1-2 amps each under heavy LVDS toggling, so each bank needs its own bulk capacitor. Use a dedicated switching regulator with 3 percent load regulation to prevent voltage droop during DSP block bursts.
The H484 FCBGA at 1.0 mm pitch requires 0.5 mm via-in-pad (VIPPO) microvias for fan-out, with staggered microvia stacks connecting inner layers. Use ENIG or ENEPIG surface finish to ensure solder joint reliability. Recommended: do not route signal traces between adjacent BGA balls under the package perimeter; route outward to break-out vias outside the BGA shadow. Critical: keep all clock and PLL feedback traces length-matched to within 100 mils.
Do not leave unused I/O pins floating: configure them as inputs with weak pull-up resistors enabled in the Quartus II pin planner to avoid random toggling. Critical: never apply voltage to any I/O before VCCINT and VCCIO rails have ramped, as latch-up can occur. For configuration, always pull MSEL0/MSEL1 to a defined logic level via 1 kohm resistor; floating MSEL pins cause configuration failure on some boards.
LVDS signals on Stratix II should be routed with 100 ohm differential impedance, matched length within 50 mils, and series-stitched 100 ohm resistors near the receiver. HSTL Class I and II outputs require external 50 ohm termination to VTT. Recommended: use IBIS models from the Quartus II library for simulation of DDR2 memory interfaces, which are particularly sensitive to reflections if stubs exceed 200 mils.
Compliance Information
RoHS compliance confirmed via Altera (Intel FPGA) product page. AEC-Q100 not applicable for FPGAs used in commercial-grade industrial equipment. Halogen-free and conflict-mineral status not specified in public datasheet; set to 'unknown' per Data Authenticity Rules.
