EP610LC-25 - 16-Macrocell Classic EPLD, 25ns, PLCC-28 | Intel
MPN: EP610LC-25 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $10.8 | $108.00 |
| 100 | $8.95 | $895.00 |
| 500 | $7.4 | $3,700.00 |
| 1,000 | $6.2 | $6,200.00 |
EP610LC-25 Overview
A Classic EPLD is a type of programmable logic device (PLD) that combines the low cost and simplicity of PAL/GAL architectures with the flexibility and density of early FPGA-like logic. In the broader taxonomy, the EP610LC-25 sits within: programmable logic device -> erasable PLD -> CMOS EPLD -> Classic EPLD family. The EP610 family was introduced in the late 1980s as one of the first UV-erasable CMOS PLDs suitable for high-speed state machine and bus-interface applications.
Key features include 16 macrocells, 25 ns maximum pin-to-pin propagation delay (tPD), a 100 MHz maximum toggle frequency, and a 5V ±5% supply requirement. The device is in-system or window-erasable (UV forcerasable ceramic windowed variants) and supports industry-standard JEDEC file formats for programming. Per the Altera Classic Device Family datasheet, the EP610 provides bidirectional I/O, programmable output enable, and configurable flip-flop polarity in every macrocell.
The architecture uses an AND/OR PLA-style logic array with a fixed OR plane feeding programmable flip-flop macrocells, providing predictable timing with no routing delay variance. Each macrocell contains a flip-flop, output polarity control, and a tri-state output buffer, enabling implementation of both combinatorial and registered logic with deterministic timing.
Typical applications include bus-interface glue logic, state-machine controllers, address decoders, and 5V legacy system replacements. The 28-pin PLCC footprint is socket-compatible with standard 28-pin PLCC sockets, enabling easy drop-in replacement of older PAL/GAL devices.
When designing with this part, designers should ensure 5V ±5% supply tolerance and provide adequate decoupling (100 nF ceramic near VCC). For new designs, modern CPLDs such as the Altera MAX II family or Lattice ispMACH 4000 series offer substantially higher logic density, lower power, and in-system programmability.
This page synthesizes distributor availability, pin-compatible alternatives from the same Classic EPLD family, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for EP610LC-25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610LC-25 (same form factor and footprint) — differing in Package, Family, Technology, Mounting Type, Supply Voltage (VCC).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610LC-15
✅ Drop-In✓ In Stock
$4.65 / Unit
View Datasheet →EP610LC-30
✅ Drop-In✓ In Stock
$16.4 / Unit
View Datasheet →EP610LC-35
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610ILC-25
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EP610ILC-10
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EP610IDC-25
✅ Drop-In📋 Reference alternative (not in catalog)
EP610LC-25 Maximum Ratings & Electrical Characteristics
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EPLD |
| Macrocells | 16 |
| Logic Array Blocks (LABs) | 4 |
| Propagation Delay (tPD) | 25 ns |
| Maximum Toggle Frequency | 100 MHz |
| Pipelined Data Rate | Up to 100 MHz |
| Supply Voltage | 5 V ±5% |
| Technology | CMOS |
| Programmability | UV-erasable (windowed package) |
| Package | PLCC-28 |
| Operating Temperature | 0C to +70C (commercial) |
| Mounting Type | Surface Mount |
EP610LC-25 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O macrocell pin |
| Pin 2 | I/O — Bidirectional I/O macrocell pin |
| Pin 3 | I/O — Bidirectional I/O macrocell pin |
| Pin 4 | I/O — Bidirectional I/O macrocell pin |
| Pin 5 | I/O — Bidirectional I/O macrocell pin |
| Pin 6 | I/O — Bidirectional I/O macrocell pin |
| Pin 7 | I/O — Bidirectional I/O macrocell pin |
| Pin 8 | I/O — Bidirectional I/O macrocell pin |
| Pin 9 | GND — Ground |
| Pin 10 | I/O — Bidirectional I/O macrocell pin |
| Pin 11 | I/O — Bidirectional I/O macrocell pin |
| Pin 12 | I/O — Bidirectional I/O macrocell pin |
| Pin 13 | I/O — Bidirectional I/O macrocell pin |
| Pin 14 | I/O — Bidirectional I/O macrocell pin |
| Pin 15 | I/O — Bidirectional I/O macrocell pin |
| Pin 16 | I/O — Bidirectional I/O macrocell pin |
| Pin 17 | I/O — Bidirectional I/O macrocell pin |
| Pin 18 | I/O — Bidirectional I/O macrocell pin |
| Pin 19 | I/O — Bidirectional I/O macrocell pin |
| Pin 20 | I/O — Bidirectional I/O macrocell pin |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — Bidirectional I/O macrocell pin |
| Pin 23 | I/O — Bidirectional I/O macrocell pin |
| Pin 24 | I/O — Bidirectional I/O macrocell pin |
| Pin 25 | I/O — Bidirectional I/O macrocell pin |
| Pin 26 | I/O — Bidirectional I/O macrocell pin |
| Pin 27 | I/O — Bidirectional I/O macrocell pin |
| Pin 28 | VCC — +5V supply |
Typical Applications
EP610LC-25 is suitable for 6 applications: Legacy 5V Bus Interface Glue Logic, State Machine Controllers for Industrial Control, Address Decoder and Chip-Select Generation, Legacy Avionics and Military Systems, Telecommunications Line Card Logic, Test Equipment and Instrumentation.
Legacy 5V Bus Interface Glue Logic
The EP610LC-25's 16 macrocells and 25 ns propagation delay make it well-suited for replacing discrete 74LS/74F TTL glue logic in legacy 5V systems such as ISA bus cards, VME bus controllers, and parallel-port interfaces. With up to 100 MHz toggle frequency and a 5V ±5% supply, the EP610LC-25 directly interfaces with 5V TTL/CMOS peripherals without level shifters. The 28-pin PLCC package fits standard IC sockets used in 1990s industrial PC/104 designs, enabling drop-in upgrade paths for EOL discrete logic.
Recommended
State Machine Controllers for Industrial Control
The EP610LC-25's deterministic 25 ns propagation delay and 16 macrocells are ideal for implementing Moore/Mealy state machines in industrial control systems. Each macrocell's programmable flip-flop and output polarity control allows efficient encoding of 4-8 state machines per device. The Classic EPLD's predictable timing (no routing delay variance) makes timing analysis straightforward versus early FPGAs, which is critical for safety-related industrial controllers where timing margins must be deterministic.
Recommended
Address Decoder and Chip-Select Generation
With 16 macrocells and 28-pin PLCC packaging, the EP610LC-25 is well-matched to address-decoding applications in 8/16-bit microcontroller or microprocessor systems. The wide AND/OR PLA-style logic array efficiently implements multi-input address comparisons, while the macrocell output enables provide independent chip-select signals. The 25 ns propagation delay adds minimal latency to system read/write cycles, preserving timing margins in legacy 5V systems where the EP610LC-25 has been deployed for decades.
Recommended
Legacy Avionics and Military Systems
The EP610LC-25 with its 28-pin PLCC package and 16-macrocell Classic EPLD architecture is found in many long-lifecycle avionics and military systems designed in the 1990s. The -25 speed grade provides adequate margin for sub-MHz control logic in flight management computers and military radios. For new designs in this domain, however, the part is obsolete and modern FPGAs (Microsemi SmartFusion or Xilinx Spartan-6Q) with MIL-PRF-38535 qualification are preferred for radiation tolerance and supply assurance.
Recommended
Telecommunications Line Card Logic
The EP610LC-25's 5V supply tolerance and 25 ns propagation delay historically supported telecom line-card logic such as T1/E1 framer control, HDLC protocol engines, and timeslot switching. Its 16 macrocells provide sufficient logic density for small protocol-state machines, while the 100 MHz toggle frequency accommodates the 1.544/2.048 MHz T1/E1 line rates with substantial timing margin. Modern telecom designs use higher-density CPLDs/FPGAs, but the EP610LC-25 remains deployed in legacy SPC switches.
Recommended
Test Equipment and Instrumentation
The EP610LC-25's programmable AND/OR array and 16 macrocells support custom waveform generation, timing-sequencer logic, and stimulus-response handlers in legacy test equipment. The deterministic 25 ns propagation delay enables precise timing control in go/no-go testers, while the UV-erasable windowed ceramic variants allow prototype development with multiple iterations. Test equipment manufacturers using 28-pin PLCC sockets can drop-in the EP610LC-25 alongside other Classic EPLD family members for mixed-speed subsystems.
Recommended
Recommended Products Summary
Engineering reference data for EP610LC-25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610LC-15 | EP610LC-30 | EP610LC-35 | EP610ILC-25 | EP610ILC-10 | EP610IDC-25 |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | PLCC-28 | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 15 ns | 30 ns | 35 ns | 25 ns | 10 ns | 25 ns |
| Max Toggle Frequency | 100 MHz | 125 MHz | 83.3 MHz | 71.4 MHz | 100 MHz | 125 MHz | 100 MHz |
| Supply Voltage | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% | 5 V ±5% |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C | -40C to +85C | -40C to +85C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Balanced 25 ns speed grade vs slower 30/35 ns variants (vs EP610LC-30)
- Commercial 0C to +70C temperature range with broad distributor availability (vs EP610ILC-25)
- Industry-standard JEDEC programming file compatibility (vs Cross-brand EPLDs)
- Proven 1990s legacy with 30+ years of field deployment (vs Modern MAX II EPM240)
Design Notes
The EP610LC-25 operates from a single 5V ±5% supply. Place a 100 nF ceramic decoupling capacitor as close as possible to the VCC pin (pin 28 on PLCC-28) and a 10 µF tantalum or aluminum bulk capacitor at the board-level supply entry. The PLCC-28 package has relatively long internal bond wires; local decoupling is critical for clean programming and reliable toggle-frequency operation at 100 MHz. Estimated: at 100 MHz toggle with all 16 outputs switching, ICC is approximately 100-150 mA per the Classic EPLD datasheet family characteristics.
The PLCC-28 package has a thermal resistance (theta_JA) of approximately 70 C/W in still air and 50 C/W with 100 LFM airflow. Estimated: at maximum ICC of 150 mA and 5.25V worst-case supply, power dissipation is about 0.79 W, yielding a 55C junction temperature rise above ambient. The part is rated for commercial 0C to +70C operation; for industrial -40C to +85C applications use the EP610ILC-25 variant in the same package.
Use a standard PLCC-28 socket (e.g., 3M Textool or Augat) for prototyping to allow easy device removal and UV-erase reprogramming. For production, the PLCC-28 can be hand-soldered with a hot-air rework station or reflow-soldered with a standard SMD profile (peak 235C for 30 seconds). The PLCC footprint pads should extend at least 1.5 mm beyond the package edge per IPC-SM-782 guidelines to ensure reliable solder fillets. Use a ground plane on the inner PCB layer directly under the device to minimize ground bounce on the high-current switching outputs.
Do not confuse the EP610LC-25 (PLCC-28) with the EP610PC-25 (PDIP-24) or EP610DC-25 (ceramic DIP-24). All three share the same die but use incompatible packages. Also note that EP610 outputs are TTL-compatible at 5V but the input thresholds are CMOS-compatible, not true TTL; for true TTL input thresholds use the EP600 or EP900 family. Finally, the JEDEC programming file generated for the LC-25 speed grade will not run on the LC-30 or LC-35 parts without recompilation, even though they share the same architecture.
Keep all PLCC-28 output traces shorter than 50 mm to minimize transmission-line reflections when driving 5V TTL loads. Series-damping resistors (22-33 ohm) near the EP610 output pins are recommended for traces longer than 25 mm driving high-capacitive loads (>50 pF). Group synchronous output traces together with matched lengths to minimize skew in clock-distribution applications. Place the programming header (for in-system or socket-programmed updates) within 50 mm of the device to allow JEDEC file downloads without signal integrity issues.
Compliance Information
EP610LC-25 is an obsolete legacy Altera/Intel part from the 1990s. RoHS, REACH, and halogen-free status were not consistently documented for the Classic EPLD family. Industrial-temp variants (EP610ILC-25, EP610IDC-25) are not AEC-Q100 qualified (not an automotive part). Compliance data unavailable in provided verified sources; consult Rochester Electronics for current compliance documentation.
