EP910JM-40 - 24-Macrocell UV EPLD, 40ns | Altera Classic
MPN: EP910JM-40 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.8 | $1,380.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP910JM-40 Overview
A UV Erasable Programmable Logic Device (UV EPLD) is a one-time-programmable (erasable via ultraviolet light through the ceramic window) PLD built on CMOS technology, belonging to the broader category of programmable logic devices (PLD) > programmable logic > logic ICs > integrated circuits (ICs). Compared with later SRAM-based FPGAs, EPLDs are non-volatile, deterministic, and feature a predictable timing model with pin-to-pin delays independent of internal routing. The EP910 sits in the mid-density Classic family, between the EP610 (16 macrocells) and EP1810 (48 macrocells), and is well suited to glue-logic integration on systems where a few hundred gates of custom logic replace discrete 74-series TTL.
Key features include 24 macrocells, 12 dedicated inputs, 24 I/O lines (36 inputs / 24 outputs maximum), 240 product terms, two external clock inputs, and CMOS low-power operation. The J-suffix (windowed ceramic JLCC) package enables field erasure and reprogramming under a UV lamp, while the -40 speed grade designates a 40 ns tPD from input pin to output pin. These specifications make the EP910JM-40 a common drop-in part for legacy designs originally prototyped on Altera or third-party EPLD toolchains.
Architecturally, the EP910 uses a sum-of-products AND/OR array feeding 24 output macrocells, each with a programmable register, output enable, and feedback path. The global bus distributes 12 dedicated inputs to all macrocells, allowing wide combinational fan-in. Designers compile logic with the Altera MAX+PLUS II or legacy A+PLUS toolchain and program the device with a standard EPROM programmer.
Typical applications include address decoding and chip-select generation in 80C186/68k/MIPS designs, bus arbitration glue logic, state-machine controllers for industrial controllers, replacement of multiple 74LS/74F TTL packages, and instrumentation front-panel logic. The 40 ns delay grade suits systems with clock periods of 100 ns or longer (e.g., 10 MHz bus architectures). When designing with this part, ensure the IC socket allows UV erasure through the quartz window, use a 25 ms erasure cycle, and verify with the EP910 family datasheet that the JTAG/programming pinout matches the programmer header.
Drop-in alternatives for EP910JM-40 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP910JM-40 (same form factor and footprint) — differing in Package, Mounting Type, Family, Architecture, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP910ILC-50
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.85 / Unit
View Datasheet →EP910ILC-25
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EP910DC-40
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$13.95 / Unit
View Datasheet →EP910DC-35
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.95 / Unit
View Datasheet →EP910DM-40
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$21 / Unit
View Datasheet →EP910JM-40 Maximum Ratings & Electrical Characteristics
| Device Family | Altera Classic EPLD |
| Series | EP910 |
| Logic Type | EPLD (UV-Erasable PAL-type) |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Lines | 24 |
| Total Inputs (max) | 36 |
| Total Outputs (max) | 24 |
| Product Terms | 240 |
| External Clock Inputs | 2 |
| Propagation Delay (tPD) | 40 ns |
| Process Technology | CMOS |
| Package | JLCC-28 (windowed ceramic, J-lead) |
| Mounting Type | Surface Mount |
| Programming Method | UV erase + EPROM programmer |
EP910JM-40 jlcc-28 (windowed ceramic, j-lead) Pin Configuration Guide
Pin configuration for EP910JM-40 (jlcc-28 (windowed ceramic, j-lead) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP910JM-40.
Refer to the datasheet for full pin configuration.
Typical Applications
EP910JM-40 is suitable for 6 applications: Address Decoding and Chip-Select Generation, Bus Arbitration Glue Logic, State-Machine Controllers for Industrial Equipment, TTL Replacement and Logic Consolidation, Instrumentation Front-Panel Logic, Legacy Peripheral Interface Adapters.
Address Decoding and Chip-Select Generation
The EP910JM-40 is well suited for address decoding and chip-select generation in 80C186, 68k, and MIPS-based systems. With 24 macrocells and 12 dedicated inputs, the device can decode 8-to-16-bit address buses with multiple output-enable control. The 240 product terms support wide fan-in AND-OR logic for memory and peripheral bank selection. Designers place the EP910JM-40 between the processor address bus and the peripheral CE pins, using the two external clock inputs for synchronous registered enables. Compared to discrete 74LS138/139 decoder trees, the EP910JM-40 consolidates logic, reduces board area, and provides software-reprogrammable (UV-erase) flexibility. The 40 ns tPD fits 10 MHz bus architectures with timing margin to spare.
Recommended
Bus Arbitration Glue Logic
The EP910JM-40 implements multi-master bus arbitration glue logic in VMEbus, Multibus, and proprietary backplane designs. Its 24 macrocells can encode 4-to-8-way arbitration priority, while the 24 I/O lines provide bus-request and bus-grant signal distribution. The two external clock inputs allow synchronized arbitration across clock domains. The CMOS low-power operation keeps standby current low, important for backplane cards with thermal constraints. The 40 ns propagation delay suits arbitration propagation for backplane clocks of 8-10 MHz. Designers replace 4-6 TTL packages with a single EP910JM-40, reducing board real-estate and improving reliability through fewer solder joints.
Recommended
State-Machine Controllers for Industrial Equipment
The EP910JM-40 functions as a state-machine controller in industrial automation equipment, where deterministic timing and CMOS noise immunity are essential. With 24 macrocells each containing a programmable flip-flop, the device implements Moore or Mealy FSMs with up to 16 million states. The two external clock inputs handle primary state-clock and asynchronous reset/clock-domain crossing. The CMOS process technology delivers 50-100 MHz toggle rates internally while consuming only milliwatts of standby power. The 40 ns tPD supports state-machine clock frequencies up to approximately 20 MHz. Industrial designers favor the EP910JM-40 over discrete 74LS/74F TTL because it consolidates 8-10 ICs into one reprogrammable device, enabling post-assembly logic changes via UV erase.
Recommended
TTL Replacement and Logic Consolidation
The EP910JM-40 replaces multiple 74LS, 74F, and 74ALS TTL packages in legacy designs, consolidating discrete glue logic into a single reprogrammable device. A single EP910JM-40 typically replaces 6-10 TTL SSI/MSI packages, including AND/OR gates, multiplexers, flip-flops, and one-shots. The 24 I/O lines interface directly with 5 V TTL logic without level shifters, and the CMOS output drive (8 mA IOL/IOH) is sufficient for bus fan-out. The UV-windowed JLCC-28 package allows field re-erasure under a UV lamp, making it ideal for prototyping where logic evolves. Designers migrating from TTL to EPLD benefit from reduced board area, lower power, and design flexibility while preserving timing margins with the 40 ns tPD specification.
Recommended
Instrumentation Front-Panel Logic
The EP910JM-40 implements front-panel keyboard scanners, display multiplexers, and switch debouncers in test-and-measurement instrumentation. Its 24 macrocells debounce up to 24 keys, scan 7-segment displays via BCD-to-7-segment logic, and generate timing waveforms for indicators. The 12 dedicated inputs accept front-panel switch matrix rows, while the 24 I/O lines drive LED column drivers and LCD enable signals. The CMOS low-power design reduces thermal load in enclosed benchtop instruments. The 40 ns delay fits keyboard scan rates of 1 kHz with substantial timing margin. Engineers use the EP910JM-40 to consolidate display drivers, key encoders, and waveform generators into a single logic device, reducing BOM and assembly cost.
Recommended
Legacy Peripheral Interface Adapters
The EP910JM-40 implements custom peripheral interface adapters that do not fit standard LSI chips. With 24 macrocells, it can emulate GPIB talker/listener handshaking, SCSI bus parity logic, or Centronics port signal conditioning. The two external clock inputs synchronize data transfer with peripheral timing. The 40 ns tPD supports Centronics-style strobe-based handshakes at 200 kbytes/s. Industrial designers prefer the EP910JM-40 for low-volume proprietary interfaces where designing an ASIC is uneconomical. The UV-erasable package allows field logic updates when customer requirements evolve, without requiring board rework.
Recommended
Recommended Products Summary
Engineering reference data for EP910JM-40 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP910ILC-50 | EP910ILC-25 | EP910DC-40 | EP910DC-35 | EP910DM-40 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | JLCC-28 (windowed) | JLCC-28 (windowed) | JLCC-28 (windowed) | JLCC-28 (windowed) | JLCC-28 (windowed) | JLCC-28 (windowed) |
| Propagation Delay (tPD) | 40 ns | 50 ns | 25 ns | 40 ns | 35 ns | 40 ns |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Dedicated Inputs | 12 | 12 | 12 | 12 | 12 | 12 |
| I/O Lines | 24 | 24 | 24 | 24 | 24 | 24 |
| Temperature Grade | Commercial (0C to +70C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Military (-55C to +125C) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Field-reprogrammable UV windowed package (vs EP910DC-40 (plastic non-windowed))
- Mid-density position in Classic family (vs EP610LI-30)
- 40 ns tPD suits 10 MHz bus architectures (vs EP910ILC-50)
Design Notes
The EP910JM-40 must be programmed via a UV-erasable EPROM programmer, NOT a JTAG programmer. Use the Altera Logic Programmer card with the A+PLUS or MAX+PLUS II software. Apply a UV erase dose of approximately 25 W-s/cm^2 at 253.7 nm (typical UV eraser) for 20-30 minutes before reprogramming. Verify erasure with a blank-check before writing; incomplete erasure can cause logic errors at startup.
Mount the EP910JM-40 in a windowed JLCC-28 socket (e.g., 3M Textool or equivalent) to allow UV erasure in-circuit. The ceramic JLCC package dissipates approximately 1 W maximum - provide thermal relief through copper pour on all GND pins. Keep the UV quartz window clear of conformal coating or labels; obstructions prevent erasure. Decouple VCC with one 0.1 uF ceramic capacitor per VCC pin and one 10 uF tantalum bulk capacitor within 1 cm of the package.
The EP910JM-40 outputs drive 8 mA IOL / -4 mA IOH, sufficient for 5 V TTL fan-out of 10-20 loads. For bus-driven outputs, enable the on-chip slew-rate control to limit ground bounce on simultaneous switching outputs. Unused I/O pins should be configured as outputs driving LOW or as inputs with internal pull-ups enabled to avoid floating-input oscillations. Maintain a 20 ns minimum setup/hold time on the two external clock inputs relative to input pins registered into macrocells.
Compliance Information
UV-windowed ceramic JLCC package typically contains leaded ceramic and is NOT RoHS compliant. Part is obsolete; compliance data not maintained by Altera/Intel PSG.
