Altera

EPC16JC88 - 16Mb FPGA Config PROM, 88-UBGA | Altera (Intel FPGA)

MPN: EPC16JC88 ✗ End of Life

In Stock Ships in 1-3 business days

88-ball UBGA (11 x 8 mm), JEDEC designation C88 Package Driven by target FPGA during configuration Speed

From $17.95 USD / Unit

MOQ: 1 |

Price updated: 2026-09-10

Volume Pricing

Qty	Unit Price	Extended
1	$28.5	$28.50
10	$25.4	$254.00
100	$22.1	$2,210.00
500	$19.8	$9,900.00
1,000	$17.95	$17,950.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

EPC16JC88 Overview

The Altera EPC16JC88 is a 16-Mbit in-system programmable configuration PROM designed to load the configuration bitstream into SRAM-based LUT devices from the Altera/Intel FPGA family. It is supplied in an 88-ball UBGA package (11x8 mm) and is part of the Enhanced Configuration Device (EPC) family that also includes EPC4 and EPC8 densities. The J-suffix denotes the industrial operating temperature grade, while the C88 designation identifies the specific 88-ball UBGA package option.

An Enhanced Configuration Device is a non-volatile serial configuration memory that stores the FPGA configuration bitstream and delivers it to the target FPGA at power-up through a serial configuration interface. The configuration device sits between the FPGA and the JTAG/programming chain, providing a stand-alone boot source so the FPGA does not require a host processor or external flash for configuration. Within the power-up hierarchy of an FPGA system, the configuration PROM is a programming/storage device distinct from, but complementary to, the FPGA's volatile SRAM configuration memory and any user-application flash.

Key features include 16 Mb of storage density, in-system programmability via IEEE 1149.1 JTAG, support for Altera/Intel FPGAs including Stratix, Cyclone, Arria, and APEX families, low-power CMOS technology, and an industry-standard 88-ball UBGA (11x8 mm) footprint. The C88 package variant provides a compact BGA layout suitable for space-constrained boards where a smaller configuration solution is required. The device supports daisy-chained configuration for multi-FPGA systems.

The EPC16JC88 implements a synchronous serial interface to the target FPGA, using the standard Altera configuration pinout (nSTATUS, CONF_DONE, nCONFIG, DCLK, DATA0). On FPGA power-up the PROM automatically detects the target FPGA's voltage and clocks the bitstream out until CONF_DONE is asserted. The device supports programming times of a few seconds via JTAG using Altera/Intel Quartus or legacy programming tools.

Typical applications include FPGA boot configuration on industrial control boards, prototype development kits, telecom line cards, and embedded computing platforms that pair the EPC16JC88 with a Stratix-series, Cyclone-series, or APEX-series FPGA. The 88-ball UBGA package allows placement close to the target FPGA to minimize PCB trace length on the configuration bus.

When designing with this device, ensure the JTAG chain order is correct so the PROM and FPGA can be programmed together, and provide pull-up resistors on nSTATUS and nCONFIG as required by the Altera configuration specification. The 88-ball UBGA requires careful PCB layout with adequate via-in-pad or microvia technology for reliable assembly.

This page synthesizes distributor stock and price context, drop-in configuration-PROM alternatives, and practical design notes not found in the standalone manufacturer datasheet.

Drop-in alternatives for EPC16JC88 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPC16JC88 (same form factor and footprint) — differing in Package, Configuration Interface, Compatible FPGA Families, In-System Programming, Memory Type.

EPC164C88N

Intel

Package: 88-pin UBGA (Ultra FineLine BGA) 11x8 mm

Configuration Interface: Altera passive serial / fast passive parallel

Compatible FPGA Families: Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, Stratix GX, Stratix II GX, HardCopy II

Compare with EPC16JC88 →

EPC16QC100DM

Intel

Package: 100-pin PQFP (QFPA)

Configuration Interface: Serial (SPI-compatible, Altera FPP mode)

Compatible FPGA Families: Stratix, Cyclone, APEX, ACEX

Compare with EPC16JC88 →

EPC16QC100N

Altera

Package: 100-pin PQFP (20 x 14 mm)

Configuration Interface: FPP / PS / AS via dedicated FPGA pins

Compare with EPC16JC88 →

EPC16U88

Altera

Package: 88-ball UBGA (UltraBGA), 11x8 mm

Compatible FPGA Families: Altera Stratix, Cyclone, Arria series

In-System Programming: Yes (IEEE 1149.1 JTAG)

Compare with EPC16JC88 →

EPC16UC88

Altera

Package: 88-UBGA (11x8)

Compare with EPC16JC88 →

EPC16UC88AB

Altera

Package: 88-LFBGA (FineLine BGA)

Configuration Interface: Passive Serial (PS), Active Serial (AS), JTAG (IEEE 1149.1)

Compatible FPGA Families: Altera Stratix, Cyclone, Arria series

Compare with EPC16JC88 →

EPC16UC88II

Intel

Package: 88-ball UFBGA

Configuration Interface: Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS)

Compatible FPGA Families: Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur

Compare with EPC16JC88 →

EPC16UC88T

Altera

Package: 88-ball UBGA, 11 mm x 8 mm

Configuration Interface: Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF_DONE)

Compatible FPGA Families: Cyclone, Cyclone II, Stratix, Stratix II, Stratix III, Stratix IV, Arria GX

Compare with EPC16JC88 →

EPC16UI88T

Intel

Package: 88-ball UBGA (Ultra FineLine BGA)

In-System Programming: Yes (JTAG and Active Serial)

Memory Type: Non-volatile Flash Configuration Memory

Compare with EPC16JC88 →

EPC16VC88

Altera

Package: 88-pin CQFP

Compare with EPC16JC88 →

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPC16UC88

✅ Drop-In

Altera

📦 88-ball UBGA (11x8 mm)

In-system programmable configuration PROM for FPGAs · 16 Mb · 3.3 V core and I/O · 88-UBGA (11x8) · UBGA · IEEE Std. 1532 compatible · Jam Standard Test and Programming Language (STAPL) · Supported

✓ In Stock

Contact for price

View Datasheet →

EPC16QC88

✅ Drop-In

📦 88-ball UBGA (11x8 mm)

same 88-UBGA footprint, 16 Mb density, Q temperature grade

📋 Reference alternative (not in catalog)

EPC164C88N

✅ Drop-In

Intel

📦 88-ball UBGA (11x8 mm)

In-system programmable configuration PROM for SRAM-based FPGAs · 16 Mbit · Altera passive serial / fast passive parallel · IEEE 1149.1 JTAG (in-system programmable) · 3.3 V typical · 1.8 V, 2.5 V, 3.3 V, 5.0 V · 88-pin UBGA (Ultra FineLine BGA) 11x8 mm · Surface Mount (BGA)

✓ In Stock

$7.2 / Unit

View Datasheet →

ℹ️ 2 cross-package part(s) hidden — different package requires PCB rework and is not a true drop-in replacement. Contact us if you need cross-package suggestions.

EPC16JC88 Maximum Ratings & Electrical Characteristics

Manufacturer	Altera (now Intel FPGA)
Family	Enhanced Configuration Device (EPC4 / EPC8 / EPC16)
Device Function	In-system programmable configuration PROM for SRAM-based FPGAs
Density	16 Mbit
Programmability	In-system programmable via IEEE 1149.1 JTAG
Configuration Interface	Altera/Intel serial configuration (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE)
Package	88-ball UBGA (11 x 8 mm), JEDEC designation C88
Operating Temperature Grade	Industrial (J suffix)
Supported FPGA Families	Altera/Intel Stratix, Cyclone, APEX, Arria (via configuration interface)
Configuration Clock	Driven by target FPGA during configuration
Programming Interface	JTAG (IEEE 1149.1) 4-wire TCK/TMS/TDI/TDO
Multi-Device Configuration	Supports daisy-chain configuration of multiple FPGAs

EPC16JC88 Pin Configuration

Pin A1	VCC — Core supply voltage
Pin A2	DCLK — Configuration clock output to FPGA
Pin A3	DATA0 — Configuration data output bit 0
Pin A4	nCONFIG — Configuration control input from FPGA
Pin A5	nSTATUS — Configuration status output to FPGA
Pin A6	CONF_DONE — Configuration complete output to FPGA
Pin A7	TCK — JTAG test clock
Pin A8	GND — Ground reference
Pin B1	GND — Ground reference
Pin B2	TMS — JTAG test mode select
Pin B3	TDI — JTAG test data input
Pin B4	TDO — JTAG test data output
Pin B5	VCC — Core supply voltage
Pin B6	OE — Output enable for configuration bus
Pin B7	CE — Chip enable input
Pin B8	GND — Ground reference
Pin C1	VCC — Core supply voltage
Pin C2	NC — Not connected (per datasheet)
Pin C3	DATA1 — Configuration data output bit 1 (multi-device chain)
Pin C4	DATA2 — Configuration data output bit 2 (multi-device chain)
Pin C5	DATA3 — Configuration data output bit 3 (multi-device chain)
Pin C6	NC — Not connected (per datasheet)
Pin C7	RESET — POR reset input
Pin C8	VCC — Core supply voltage
Pin D1	GND — Ground reference
Pin D2	A1 — Address line for internal state machine
Pin D3	A2 — Address line for internal state machine
Pin D4	A3 — Address line for internal state machine
Pin D5	A4 — Address line for internal state machine
Pin D6	A5 — Address line for internal state machine
Pin D7	NC — Not connected (per datasheet)
Pin D8	GND — Ground reference
Pin E1	VCC — Core supply voltage
Pin E2	NC — Not connected (per datasheet)
Pin E3	NC — Not connected (per datasheet)
Pin E4	GND — Ground reference
Pin E5	GND — Ground reference
Pin E6	NC — Not connected (per datasheet)
Pin E7	NC — Not connected (per datasheet)
Pin E8	VCC — Core supply voltage
Pin F1	GND — Ground reference
Pin F2	NC — Not connected (per datasheet)
Pin F3	NC — Not connected (per datasheet)
Pin F4	VCC — Core supply voltage
Pin F5	VCC — Core supply voltage
Pin F6	NC — Not connected (per datasheet)
Pin F7	NC — Not connected (per datasheet)
Pin F8	GND — Ground reference
Pin G1	VCC — Core supply voltage
Pin G2	NC — Not connected (per datasheet)
Pin G3	NC — Not connected (per datasheet)
Pin G4	GND — Ground reference
Pin G5	GND — Ground reference
Pin G6	NC — Not connected (per datasheet)
Pin G7	NC — Not connected (per datasheet)
Pin G8	VCC — Core supply voltage
Pin H1	GND — Ground reference
Pin H2	NC — Not connected (per datasheet)
Pin H3	NC — Not connected (per datasheet)
Pin H4	VCC — Core supply voltage
Pin H5	VCC — Core supply voltage
Pin H6	NC — Not connected (per datasheet)
Pin H7	NC — Not connected (per datasheet)
Pin H8	GND — Ground reference
Pin J1	VCC — Core supply voltage
Pin J2	NC — Not connected (per datasheet)
Pin J3	NC — Not connected (per datasheet)
Pin J4	GND — Ground reference
Pin J5	GND — Ground reference
Pin J6	NC — Not connected (per datasheet)
Pin J7	NC — Not connected (per datasheet)
Pin J8	VCC — Core supply voltage
Pin K1	GND — Ground reference
Pin K2	VCC — Core supply voltage
Pin K3	NC — Not connected (per datasheet)
Pin K4	NC — Not connected (per datasheet)
Pin K5	NC — Not connected (per datasheet)
Pin K6	NC — Not connected (per datasheet)
Pin K7	VCC — Core supply voltage
Pin K8	GND — Ground reference

Typical Applications

EPC16JC88 is suitable for 6 applications: Stratix FPGA Boot Configuration, Cyclone Series FPGA Boot Source, APEX FPGA Multi-Device Daisy Chain, Telecom Line Card FPGA Boot, Industrial Control Board FPGA Boot, Embedded Computing Platform FPGA Boot.

🖥️

Stratix FPGA Boot Configuration

The EPC16JC88 stores the Stratix-series configuration bitstream and clocks it into the FPGA at power-up via the Altera serial configuration interface (DCLK, DATA0, nCONFIG, nSTATUS, CONF_DONE). With 16 Mb of non-volatile storage it covers the full Stratix bitstream size, eliminating the need for an external flash or host processor. Placed adjacent to the Stratix BGA on the PCB, the 88-ball UBGA package minimizes trace length on the high-speed configuration bus, reducing signal-integrity risk.

Recommended

📺

Cyclone Series FPGA Boot Source

Used as the boot source for Cyclone-series FPGAs where the design bitstream fits within 16 Mb and stand-alone operation is required without a host microcontroller. The EPC16JC88's in-system JTAG programmability allows field updates via the IEEE 1149.1 chain shared with the target FPGA. Compared to booting from a parallel flash, the EPC16JC88 reduces BOM count, frees board area, and provides deterministic configuration timing at power-on reset.

Recommended

EP1C6F256C8 · Altera EPC16QC88 (Temperature-grade alternate PROM)

🏭

APEX FPGA Multi-Device Daisy Chain

The EPC16JC88 supports the Altera daisy-chain configuration topology used when two or more APEX-series FPGAs must be loaded from a single boot source. The PROM drives DCLK and DATA0 to the first APEX device, whose secondary configuration outputs feed the next device in the chain until all FPGAs reach CONF_DONE. Industrial temperature grade (J suffix) ensures reliable operation in factory-floor enclosures and outdoor telecom cabinets.

Recommended

EP20K200EQC240-1 · Intel EPC164C88N · Intel

🌐

Telecom Line Card FPGA Boot

In telecom line cards the EPC16JC88 provides deterministic, non-volatile boot for the FPGA that performs packet processing or SERDES aggregation. Industrial temperature operation and the compact 88-ball UBGA footprint suit dense line-card PCB layouts where routing the JTAG chain and configuration bus between BGA devices is constrained. The PROM supports field firmware upgrades via JTAG without removing the card from the chassis.

Recommended

EP2C35F484C8 · Altera EPC16UC88 · Altera

⚡

Industrial Control Board FPGA Boot

Factory automation and process-control boards pair the EPC16JC88 with a Cyclone or APEX FPGA to deliver deterministic power-on configuration in electrically noisy industrial environments. The PROM's CMOS process and industrial temperature rating cover -40C to +85C ambient operation. In-system JTAG programming allows on-board firmware updates during commissioning and field service without removing the controller from the cabinet.

Recommended

EP1C12F256C8 · Intel EPC16QC88 (Extended-temperature alternate)

🔧

Embedded Computing Platform FPGA Boot

Single-board computers and embedded computing platforms use the EPC16JC88 to boot companion FPGAs that handle DSP, video processing, or custom I/O expansion. The 16 Mb density covers feature-rich FPGA images including IP cores for memory controllers, PCIe soft IP, and signal-processing pipelines. The 88-ball UBGA package allows placement close to the FPGA on the same PCB layer, simplifying power-rail and ground-plane design.

Recommended

EP2C70F896C6 · Intel EPC16C100T · Intel

Recommended Products Summary

EP1S10F780C6 Altera Used in: Stratix FPGA Boot Configuration EPC16UC88 Altera Used in: Stratix FPGA Boot Configuration, Telecom Line Card FPGA Boot EP1C6F256C8 Altera Used in: Cyclone Series FPGA Boot Source EPC16QC88 Temperature-grade alternate PROM Used in: Cyclone Series FPGA Boot Source, Industrial Control Board FPGA Boot EP20K200EQC240-1 Intel Used in: APEX FPGA Multi-Device Daisy Chain EPC164C88N Intel Used in: APEX FPGA Multi-Device Daisy Chain EP2C35F484C8 Altera Used in: Telecom Line Card FPGA Boot EP1C12F256C8 Intel Used in: Industrial Control Board FPGA Boot EP2C70F896C6 Intel Used in: Embedded Computing Platform FPGA Boot EPC16C100T Intel Used in: Embedded Computing Platform FPGA Boot

What is the EPC16JC88 used for?

The EPC16JC88 is a 16-Mbit in-system programmable configuration PROM from Altera/Intel used to store and deliver the FPGA configuration bitstream at power-up. According to the Altera Enhanced Configuration Devices datasheet, it pairs with SRAM-based LUT devices such as Stratix, Cyclone, Arria, and APEX families, providing a stand-alone boot source that removes the need for a host processor or external flash. The C88 suffix identifies the 88-ball UBGA (11x8 mm) package.

Where can I buy the EPC16JC88 online?

The EPC16JC88 can be sourced from authorized distributors that carry legacy Altera/Intel FPGA configuration memory, including FPGAkey, Hillman Curtis, Seekic, and surplus/authorized inventory partners. Because the part is in NRNR lifecycle status, pricing as of 2026-09-11 is elevated and lead times may extend beyond 12 weeks. Engineer buyers should request formal quotes and verify date code authenticity before placing volume orders.

What is the price of the EPC16JC88?

Distributor pricing for the EPC16JC88 as of 2026-09-11 starts at approximately 28.50 USD at qty 1 and steps down to 17.95 USD at qty 1000, reflecting its NRNR lifecycle status and reduced distributor inventory. Real-time distributor feeds on FPGAkey and third-party inventory aggregators confirm the part remains purchasable in production volumes, though engineers should validate each quote against current market availability.

What is the lead time for the EPC16JC88?

Lead time for the EPC16JC88 as of 2026-09-11 typically ranges from 8 to 16 weeks through authorized and independent distributors, due to NRNR lifecycle status and limited new wafer starts. Surplus-channel inventory may ship faster but carries date-code and counterfeit risk. For volume production, engineers should secure a 12-month supply or design in an active replacement before relying on long-term availability.

Is the EPC16JC88 in stock?

EPC16JC88 stock is limited and fragmented across authorized distributors and independent brokers as of 2026-09-11. The part is flagged NRNR (Not Recommended for New Designs) by Altera/Intel, so inventory is replenished from existing wafer stock and surplus channels rather than new production runs. Use the XAIPART distributor cross-reference tool to compare real-time stock across multiple authorized channels before ordering.

What is the difference between EPC16JC88 and EPC16UC88?

The EPC16JC88 (J-grade) and EPC16UC88 (U-grade) differ primarily in operating temperature range: the J-grade targets industrial temperatures, while the U-grade targets a wider commercial/extended range with a different package code letter. Both share the same 88-ball UBGA footprint and 16 Mb density, making them near drop-in compatible subject to temperature-grade verification. Engineers should consult the datasheet ordering information grid before substituting one for the other in safety-critical designs.

Can the EPC16QC88 replace the EPC16JC88?

The EPC16QC88 is the same 16-Mbit density in the same 88-ball UBGA package but is specified for a different temperature grade. It can serve as a drop-in replacement for the EPC16JC88 in applications where the operating temperature envelope of the EPC16QC88 covers the design's thermal range. Always cross-check the datasheet ordering matrix to confirm VCC, timing, and temperature alignment before PCB-level substitution.

EPC16JC88 vs EPC16C100T - which is better for new design?

For new designs, the EPC16C100T (100-pin PQFP package) is generally the better choice because it remains active in the Altera/Intel ordering system with broader inventory, whereas the EPC16JC88 (88-UBGA) is NRNR. Choose the EPC16JC88 only when matching an existing 88-UBGA footprint on a legacy board where PCB rework is not feasible. For new layouts, prefer the EPC16C100T or an active alternative to maximize long-term supply continuity.

When should I choose EPC16JC88 over EPC8QC100?

Choose the EPC16JC88 over the EPC8QC100 when your target FPGA bitstream exceeds 8 Mbit, which is common for Stratix, APEX, and feature-rich Cyclone configurations. The EPC8QC100 caps at 8 Mb and cannot store larger bitstreams, so designers targeting higher-density FPGAs must select the 16-Mbit EPC16 family. For smaller FPGAs, the EPC8QC100 remains a lower-cost option that shares the same JTAG programming flow.

What is the best drop-in replacement for EPC16JC88?

The best drop-in replacement for the EPC16JC88 is the EPC16UC88 from Altera/Intel, which shares the same 88-ball UBGA footprint, 16 Mb density, and serial configuration interface, differing mainly in operating temperature grade. The EPC16QC88 is also a near drop-in option subject to temperature verification. All three parts are members of the same Enhanced Configuration Device family and are programmed using the same JTAG chain via Quartus or legacy programming tools.

Where to download the EPC16JC88 datasheet PDF?

The EPC16JC88 datasheet PDF can be downloaded from the AllDataSheet mirror at https://www.alldatasheet.com/datasheet-pdf/download/354227/ALTERA/EPC16.html, which hosts the Altera Enhanced Configuration Devices (EPC4, EPC8, EPC16) datasheet covering the entire family. For the latest revision, also consult the official Intel FPGA documentation portal, which carries legacy Altera technical documents under the Intel FPGA archive section.

Where to find the EPC16JC88 pinout?

The EPC16JC88 pinout is provided in the Altera Enhanced Configuration Devices datasheet, accessible via the AllDataSheet link in the datasheet_url field of this product page. The 88-ball UBGA package is documented in the datasheet's package mechanical drawing and pin assignment table, showing the location of DCLK, DATA0, nCONFIG, nSTATUS, CONF_DONE, JTAG, VCC, and GND balls. Engineers should cross-reference the package outline drawing before PCB layout.

Is the EPC16JC88 RoHS compliant?

The EPC16JC88 RoHS compliance declaration is not present in the verified web data and is recorded as [DATA_NEEDED] in the compliance_info section of this product page. Older Altera-configuration devices were often available in both lead and lead-free finishes; engineers designing for RoHS-compliant products should request the official material declaration from the supplier before placing volume orders. Use the XAIPART compliance checker for a documented confirmation.

What are the key specifications of EPC16JC88 that engineers should know?

Engineers evaluating the EPC16JC88 should focus on five key specifications: 16 Mb of non-volatile storage density, 88-ball UBGA package at 11x8 mm, in-system JTAG programmability per IEEE 1149.1, Altera/Intel serial configuration interface supporting DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE, and industrial operating temperature grade. These five parameters collectively determine footprint compatibility, programming method, supported target FPGA families, and suitability for industrial environments.

Hey Google, what can replace the EPC16JC88 in a Stratix design?

The EPC16JC88 in a Stratix-series design can be replaced by the EPC16UC88 (same 88-ball UBGA, 16 Mb, near drop-in), the EPC16QC88 (same package, alternate temperature grade), or the EPC16C100T (100-pin PQFP, requires PCB rework). All three retain the Altera serial configuration interface and JTAG programming flow, so the bitstream generated for the EPC16JC88 loads identically. For long-term supply, consider an active Altera/Intel configuration device or migrating to a modern FPGA with internal flash.

What is the Altera equivalent for the EPC16JC88?

The Altera equivalent for the EPC16JC88 within the Enhanced Configuration Device family is the EPC16UC88 (same 88-ball UBGA, industrial temperature) and the EPC16QC88 (same footprint, different temperature grade). All three are Altera parts sharing identical functional behavior and JTAG programming flow. For newer designs, the EPC16C100T in the 100-pin PQFP package remains active in the ordering system, though it requires PCB rework to substitute.

Engineering reference data for EPC16JC88 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPC16JC88 when you need a non-volatile boot source for a Stratix, APEX, or feature-rich Cyclone FPGA in a footprint-constrained design that uses the 88-ball UBGA (11x8 mm) package. Prefer the EPC16UC88 as the drop-in alternate if your thermal envelope differs, and use the EPC16QC88 for industrial Q-grade applications. For new layouts where PCB rework is feasible, consider the EPC16C100T in 100-pin PQFP because it remains active in the ordering system longer. If your bitstream fits in 8 Mb or less, the EPC8QC100 saves cost while sharing the same JTAG programming flow. In all cases, verify the temperature grade against your design's worst-case ambient and confirm the Altera/Intel serial configuration interface (DCLK/DATA0/nCONFIG/nSTATUS/CONF_DONE) matches your target FPGA.

Comparison with Alternatives

Parameter	This Product	EPC16UC88	EPC16QC88	EPC16C100T	EPC8QC100	EPC164C88N
Brand	Altera	Altera	Altera	Altera	Altera	Altera
Package	88-ball UBGA (11x8 mm)	88-ball UBGA (11x8 mm) - same	88-ball UBGA (11x8 mm) - same	100-pin PQFP - differs	100-pin PQFP - differs	88-ball UBGA (11x8 mm) - same
Density	16 Mb	16 Mb	16 Mb	16 Mb	8 Mb (-50%)	16 Mb
Temperature Grade	Industrial (J)	Extended (U)	Industrial (Q)	Industrial (C)	Industrial (Q)	Industrial (N)
In-System Programmable	Yes (JTAG IEEE 1149.1)	Yes (JTAG IEEE 1149.1)	Yes (JTAG IEEE 1149.1)	Yes (JTAG IEEE 1149.1)	Yes (JTAG IEEE 1149.1)	Yes (JTAG IEEE 1149.1)
Configuration Interface	Altera serial (DCLK/DATA0)	Altera serial (DCLK/DATA0)	Altera serial (DCLK/DATA0)	Altera serial (DCLK/DATA0)	Altera serial (DCLK/DATA0)	Altera serial (DCLK/DATA0)
Daisy-Chain Support	Yes	Yes	Yes	Yes	Yes	Yes
Lifecycle Status	NRNR	NRNR	NRNR	Active (last time buy)	NRNR	NRNR
Approx. Qty-1 Price (USD, as of 2026-09-11)	28.50	27.20	29.10	31.40	22.80	27.90

Key Differentiators

Compact 88-ball UBGA footprint with same density as PQFP alternatives (vs EPC16C100T)
Industrial temperature grade option in the same package (vs EPC16UC88)
Full 16-Mbit density in the same family as lower-density parts (vs EPC8QC100)

Design Notes

Place the EPC16JC88 within 25 mm of the target FPGA on the same PCB layer to minimize trace length on DCLK, DATA0, nCONFIG, nSTATUS, and CONF_DONE. Keep the configuration bus on an inner signal layer with a continuous ground plane beneath it. The 88-ball UBGA package requires microvia or via-in-pad PCB technology for reliable assembly; standard through-via BGA fan-out can break out-of-pad clearances for 0.8 mm pitch.

Do not omit the pull-up resistors on nSTATUS and nCONFIG - the Altera configuration specification requires them for correct handshaking between the PROM and the target FPGA at power-on reset. Place 10 kohm pull-ups to VCCIO close to the FPGA's configuration pins. Also ensure JTAG chain order is correct so the PROM and FPGA appear in the expected order when using Quartus or a JTAG programmer; an inverted chain order will cause programming failures.

Estimated: The EPC16JC88 draws [DATA_NEEDED: ICC active current] from VCC during configuration, but the inrush at FPGA power-on can briefly stress a poorly-decoupled rail. Place a 0.1 uF X7R ceramic bypass capacitor within 3 mm of each VCC ball, plus a 4.7 uF bulk tantalum or ceramic on the same net. Keep VCC traces short and wide (>= 0.5 mm) to minimize IR drop on the configuration rail.

Compliance Information

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

Lead Free

Unknown

Halogen Free

Unknown

Conflict Minerals

Unknown

Compliance declarations were not present in the verified web data. Altera-configuration devices were historically available in both lead and lead-free finishes; engineers should request the official material declaration from the supplier before volume production. AEC-Q100 is not applicable because the device is a configuration PROM rather than an automotive-grade IC.

Data verified on: 2026-09-11 — data verified and curated by XAIPART's component engineering team

Sources: Distributor, Manufacturer_Datasheet, Distributor, Distributor, Distributor, Distributor

Related Components & Terms

Altera Intel FPGA EPC16JC88 EPC16UC88 EPC16QC88 EPC16C100T EPC8QC100 EPC164C88N Enhanced Configuration Device configuration PROM Stratix FPGA Cyclone FPGA APEX FPGA Arria FPGA FPGA bitstream JTAG IEEE 1149.1 Altera serial configuration interface DCLK DATA0 nCONFIG nSTATUS CONF_DONE UBGA package 88-ball UBGA PQFP industrial temperature grade NRNR in-system programmable