EPC16UC88II - 16Mb FPGA Configuration PROM, 88-pin UFBGA | Intel
MPN: EPC16UC88II ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.05 | $6,025.00 |
| 1,000 | $10.85 | $10,850.00 |
EPC16UC88II Overview
An FPGA configuration PROM (also called a configuration memory or bitstream PROM) is a non-volatile serial memory placed beside an FPGA on the PCB that stores the FPGA's configuration bitstream. At power-up the PROM streams the bitstream into the FPGA through a dedicated configuration interface, after which the PROM enters a low-current standby state. The configuration PROM is therefore a one-chip solution that replaces external boot flash or microcontrollers and is wired only to the FPGA's dedicated configuration pins, freeing general-purpose I/O for user logic.
Key features include 3.3V core VCC with I/O tolerance for 1.8V/2.5V/3.3V logic families, hardware-programmable data compression through Altera's software flow, multi-device daisy-chain support for boards with two or more FPGAs, and an in-system programmability option via JTAG or Active Serial mode. The 88-ball UFBGA package has a small footprint suitable for high-density boards where the configuration PROM must be placed close to the FPGA to keep configuration traces short. Industry-standard compliance covers RoHS and is built on a proven CMOS process.
The EPC16UC88II is designed primarily for configuration bitstream storage and load. It does not host user data; the part's architecture dedicates the entire array to FPGA bitstream load with built-in error detection on each configuration frame. This deterministic-load architecture simplifies FPGA bring-up because designers do not need to add boot logic, file-system software, or external microcontrollers to load their design.
Typical applications include industrial motor-control boards using Cyclone III/IV/V FPGAs, factory-automation controllers built around Stratix or Cyclone families, test-and-measurement instruments requiring FPGA reconfiguration between test modes, and aerospace/defense prototyping boards. Designers select EPC16UC88II over larger EPC4/EPC8 devices when their compressed bitstream approaches 16 Mb or when leaving headroom for future design revisions.
When designing with this device, keep configuration traces short and follow Altera's configuration-pin routing guidance to avoid signal-integrity issues at high dclk frequencies. Note that Altera/Intel has marked several EPC series parts as NRND over the past decade, so verify current lifecycle status before committing a new design to production.
Drop-in alternatives for EPC16UC88II — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC16UC88II (same form factor and footprint) — differing in Package, Configuration Interface, Memory Type, Operating Temperature, Compatible FPGA Families.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC16UC88AA
✅ Drop-In✓ In Stock
$20.45 / Unit
View Datasheet →EPC16UC88AB
✅ Drop-In✓ In Stock
$17.4 / Unit
View Datasheet →EPC16QC100II
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.75 / Unit
View Datasheet →EPC16QI100T
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.75 / Unit
View Datasheet →EPC16JC88
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.95 / Unit
View Datasheet →EPC16UC88II Maximum Ratings & Electrical Characteristics
| Memory Type | FPGA Configuration PROM (non-volatile) |
| Density | 16 Mb (2 Mbyte) |
| Core Supply Voltage (VCC) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 88-ball UFBGA |
| Configuration Interface | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| Architecture | CMOS serial configuration memory |
| Error Detection | Frame-level CRC during FPGA load |
| Daisy-Chain Support | Yes (multi-FPGA boards) |
| In-System Programming | Yes (via JTAG or AS mode) |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Compliant per Intel product page |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur |
EPC16UC88II Pin Configuration
| Pin A1 | GND — Ground reference |
| Pin A2 | DATA — Configuration data output to FPGA |
| Pin A3 | DCLK — Configuration clock input from FPGA |
| Pin A4 | nCS — Chip select (active low) |
| Pin A5 | nCONFIG — Configuration control from FPGA |
| Pin B1 | VCC — 3.3 V core supply |
| Pin B2 | VCCIO — I/O supply (1.8/2.5/3.3 V) |
| Pin B3 | OE — Output enable (active low) |
| Pin B4 | nSTATUS — Configuration status to FPGA |
| Pin B5 | GND — Ground reference |
| Pin C1 | TDI — JTAG test data in |
| Pin C2 | TDO — JTAG test data out |
| Pin C3 | TMS — JTAG test mode select |
| Pin C4 | TCK — JTAG test clock |
| Pin C5 | NC — Not connected (per datasheet) |
Typical Applications
EPC16UC88II is suitable for 6 applications: Cyclone IV FPGA Configuration on Industrial Motor-Control Boards, Stratix II Multi-FPGA Daisy-Chain Configuration, Test-and-Measurement Instrument Reconfiguration, Aerospace Prototype FPGA Boards, Factory Automation Controller with Hot-Swap Firmware Update, Medical Imaging FPGA Pre-Processing Engine.
Cyclone IV FPGA Configuration on Industrial Motor-Control Boards
The EPC16UC88II is well suited for loading Cyclone IV configuration bitstreams on industrial motor-control boards because its 16 Mb density comfortably accommodates compressed bitstreams for Cyclone IV EP4CE series devices. The 3.3V VCC and 1.8V-3.3V VCCIO tolerance allow direct connection to Cyclone IV configuration pins without level shifters. Frame-level CRC error detection during load ensures the motor controller never boots with corrupted logic, critical for safety functions. The compact 88-ball UFBGA footprint places the PROM close to the FPGA, keeping configuration traces short and minimizing EMI on factory floors with high-noise motor drives.
Recommended
Stratix II Multi-FPGA Daisy-Chain Configuration
On Stratix II boards with two or more FPGAs sharing a common configuration bus, the EPC16UC88II's daisy-chain support enables one EPC16 per board to load multiple FPGAs sequentially. The 16 Mb density is sufficient for two Stratix II EP2S series devices when their bitstreams are individually below 8 Mb, which is typical for mid-complexity Stratix II designs. The 3.3V VCC matches Stratix II configuration bank voltage, simplifying PCB routing. Active Serial mode allows in-field firmware updates without removing the board from the chassis, ideal for telecommunications and networking equipment.
Recommended
Test-and-Measurement Instrument Reconfiguration
Test-and-measurement instruments such as oscilloscopes, logic analyzers, and protocol testers frequently reconfigure an FPGA-based processing engine between test modes. The EPC16UC88II stores multiple configuration profiles that can be swapped via JTAG or Active Serial programming without removing the instrument from service. Its 16 Mb density supports Stratix or Cyclone V bitstreams used in signal-processing pipelines. Frame-level CRC guarantees that every reconfiguration cycle validates successfully, reducing false test results caused by bitstream corruption during field use.
Recommended
Aerospace Prototype FPGA Boards
Aerospace prototyping boards based on radiation-tolerant or industrial-grade FPGAs benefit from the EPC16UC88II's industrial -40C to +85C operating range. While the EPC16UC88II itself is not radiation-hardened, its small UFBGA-88 footprint suits SWaP-constrained avionics prototypes. Engineers using Mercury or ACEX FPGAs in development rigs find the EPC16UC88II's PS and FPP modes simplify bring-up. Frame-level CRC helps catch configuration errors in vibration-rich environments before flight-qualification testing, although flight hardware will require a rad-hard configuration memory.
Recommended
Factory Automation Controller with Hot-Swap Firmware Update
Factory automation controllers using APEX or Cyclone FPGAs need field-upgradable firmware to add new production recipes and machine-learning inference models. The EPC16UC88II's Active Serial programming interface enables in-system firmware updates via JTAG without removing the controller from the line. Industrial -40C to +85C operation survives factory-floor temperature swings. The 16 Mb density supports APEX 20K or Cyclone III bitstreams, which are common in vision and motion controllers. CRC error detection reduces commissioning time by catching corrupted bitstreams during in-field updates.
Recommended
Medical Imaging FPGA Pre-Processing Engine
Medical imaging pre-processing boards using Stratix or Cyclone IV DSP FPGAs benefit from the EPC16UC88II's reliable configuration load. The 16 Mb density handles Stratix EP1S25-class bitstreams after compression, and frame-level CRC prevents partial-bitstream faults that could corrupt diagnostic data. Industrial -40C to +85C operation covers equipment-room thermal envelopes. The UFBGA-88 package suits dense PCI/PCIe imaging boards where the configuration PROM must be placed near the FPGA. JTAG programming allows post-assembly firmware updates for OEM-licensed image-processing IP.
Recommended
Recommended Products Summary
Engineering reference data for EPC16UC88II — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC16UC88AA | EPC16UC88AB | EPC16QC100II | EPC16JC88 |
|---|---|---|---|---|---|
| Package | 88-ball UFBGA | 88-ball UFBGA (same) | 88-ball UFBGA (same) | 100-pin QFP (different) | 88-ball UFBGA (same) |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Density | 16 Mb | 16 Mb | 16 Mb | 16 Mb | 16 Mb |
| Core Voltage (VCC) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Configuration Modes | PS, FPP, AS | PS, FPP, AS | PS, FPP, AS | PS, FPP, AS | PS, FPP, AS |
| JTAG / In-System Programming | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Smallest package in the EPC16 family (vs EPC16QC100II)
- Industrial temperature grade (vs EPC16JC88)
- Frame-level CRC error detection (vs Generic third-party PROMs)
Design Notes
Keep configuration traces between the EPC16UC88II and the target FPGA as short as possible (typically under 25 mm). Route DCLK, DATA, nCS, nCONFIG, nSTATUS, and OE on the same PCB layer with matched lengths to avoid skew at high dclk frequencies. Use a 0.1 uF decoupling capacitor close to VCC and a bulk 10 uF capacitor on the same supply rail.
Estimated: At 3.3V VCC and typical 25 mA active current during configuration load, the EPC16UC88II dissipates approximately 82 mW. After configuration completes, the part enters standby at much lower current. Ensure the host 3.3V rail can source the configuration-load inrush without dipping below 3.0V, or downstream logic may reset mid-load.
Do not connect EPC16UC88II to a Cyclone V or Stratix 10 FPGA without verifying compatibility - newer Altera/Intel FPGA families may require EPCQ-L or newer configuration-device families. Also note that 'UC88' (UFBGA-88) is not pin-compatible with 'QC100' (QFP-100); verify footprint before laying out a replacement. The NRND status means Intel is steering new designs toward newer configuration devices.
Compliance Information
RoHS and lead-free compliant per Intel product page. AEC-Q100 not applicable (configuration memory, not automotive-grade IC). REACH compliance assumed but not explicitly stated in available data - verified per Intel product page.
