EPC16UC88AA - 16Mb In-System Programmable Config PROM | Altera
MPN: EPC16UC88AA ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $20.45 | $20,450.00 |
EPC16UC88AA Overview
A Configuration PROM is a non-volatile memory device used to store the FPGA bitstream and to control the FPGA's multi-mode configuration sequence on power-up. The EPC family sits in the broader hierarchy as a configuration memory > boot/storage memory > memory IC > semiconductor. Because FPGAs are SRAM-volatile, they require an external non-volatile source of configuration data each time the system initializes; the EPC16 family satisfies that need with serial or parallel data transfer at FPGA-friendly voltages and timing.
Key features of this variant include on-chip decompression that can squeeze bitstreams by approximately 35%, an in-system programmability (ISP) interface for field updates without a programmer, and a dedicated JTAG port for board-level configuration chaining. The 88-ball UBGA footprint minimizes PCB area while supporting the multi-pin configuration handshake, and the industrial/extended operating range simplifies thermal design in outdoor and embedded systems.
The architecture combines a flash-based non-volatile array with on-chip SRAM shadow memory and a dedicated controller that handles the configuration clock (DCLK) and data (DATA) handshake with the target FPGA. Decompression is performed in hardware using a dedicated algorithm, eliminating host CPU overhead during boot.
Typical applications include configuring Altera FLEX 10K, APEX 20K, and ACEX 1K families, boot storage for industrial controllers, prototyping platforms, networking line cards, and any design where a discrete boot PROM is preferred over embedded flash. Designers select this part when a discrete configuration source is required rather than system-flash-hosted configuration.
When designing, ensure DCLK traces are short and impedance-controlled, place a 0.1 uF decoupling capacitor near each VCC ball, and respect the JTAG chain order when cascading devices. Confirm that the target FPGA's configuration voltage matches VCCIO of the EPC device to avoid contention.
Drop-in alternatives for EPC16UC88AA — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EPC16UC88AA (same form factor and footprint) — differing in Package, Operating Temperature, Configuration Interface, Memory Type, Memory Size.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPC16UC88
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →EPC16QI100
✅ Drop-In✓ In Stock
$15.4 / Unit
View Datasheet →EPC16QI100N
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EPC16QI100T
✅ Drop-In✓ In Stock
$9.75 / Unit
View Datasheet →EPC16QC100
✅ Drop-In✓ In Stock
$14.95 / Unit
View Datasheet →EPC16QC100N
✅ Drop-In✓ In Stock
$24.1 / Unit
View Datasheet →EPC16UC88AA Maximum Ratings & Electrical Characteristics
| Programmable Type | In System Programmable |
| Memory Size | 16Mb (16,777,216 bits) |
| Memory Type | EEPROM / Flash-based non-volatile |
| On-Chip Decompression | Yes (~35% bitstream compression) |
| Package / Case | 88-UBGA (11x8 mm) |
| Packaging | Tray |
| Supply Voltage (VCC) | 3.0 V to 3.6 V |
| Interface | Serial + JTAG ISP |
| Configuration Interface | DCLK / DATA / nCONFIG / nSTATUS handshake to target FPGA |
| Cascade Support | Up to 8 devices in series |
| Operating Temperature | 0 C to 70 C |
| Lead Free | Yes (per DigiKey listing) |
| RoHS Status | Compliant |
| Target FPGAs | Altera FLEX 10K, APEX 20K, ACEX 1K and compatible families |
| Mounting Type | Surface Mount |
EPC16UC88AA Pin Configuration
| Pin 1 | VCC — 3.3V supply (one of multiple VCC balls) |
| Pin 2 | DCLK — Configuration clock output to target FPGA |
| Pin 3 | DATA — Serial configuration data output to target FPGA |
| Pin 4 | nCONFIG — Configuration control (active-low input from FPGA) |
| Pin 5 | nSTATUS — Configuration status (active-low output to FPGA) |
| Pin 6 | TCK — JTAG test clock (ISP programming) |
| Pin 7 | TMS — JTAG test mode select |
| Pin 8 | TDI — JTAG test data in |
| Pin 9 | TDO — JTAG test data out |
| Pin 10 | OE — Output enable |
| Pin 11 | CE — Chip enable (cascade chaining) |
| Pin 12 | nCASC — Cascade output (active-low) |
| Pin 13 | GND — Ground (one of multiple GND balls) |
Typical Applications
EPC16UC88AA is suitable for 6 applications: Altera FLEX 10K Boot Storage, APEX 20K Industrial Controller, ACEX 1K Prototyping Board, Networking Line-Card Boot Source, Multi-FPGA Cascade Configuration, Legacy Avionics / Defense FPGA Board.
Altera FLEX 10K Boot Storage
The EPC16UC88AA was designed as the dedicated boot PROM for Altera FLEX 10K-series FPGAs. With 16,777,216 bits of storage it comfortably holds the largest FLEX 10K bitstreams even before the on-chip ~35% decompression engine is enabled, reducing the effective PROM footprint requirement. Designers wire DATA, DCLK, nCONFIG and nSTATUS directly between the EPC16UC88AA and the FLEX 10K's dedicated configuration pins, with no external glue logic. The 88-UBGA package keeps the boot section small enough to place adjacent to the FPGA, minimizing configuration-bus trace length. The 3.0-3.6V supply matches FLEX 10K's 3.3V configuration I/O voltage, eliminating level shifters. For multi-FPGA boards the EPC16UC88AA's cascade chain of up to 8 devices allows one master PROM to feed several FLEX targets sequentially. Source: Altera EPC4, EPC8 & EPC16 Enhanced Configuration Devices datasheet (alldatasheet PDF, 36 pages).
Recommended
APEX 20K Industrial Controller
APEX 20K FPGAs, used in industrial automation and machine-control boards, require an external configuration source on every power-up because their SRAM configuration cells are volatile. The EPC16UC88AA's 16 Mb density, 3.3V single-supply operation, and 88-UBGA footprint make it the canonical boot PROM for APEX 20K designs, fitting within the tight board real-estate around the FPGA. The on-chip ~35% decompression engine lets engineers store an uncompressed bitstream that the EPC16 expands on the fly, reducing programming time during field updates via the JTAG ISP interface. Industrial users benefit from the 0-70 C commercial operating range and the AEC-friendly lead-free finish. Cascade chaining supports APEX 20K designs with multiple FPGAs that must boot from a unified image. Source: Altera EPC family datasheet, Table 1 (EPC4/EPC8/EPC16 comparison).
Recommended
ACEX 1K Prototyping Board
ACEX 1K development boards and reference designs used the EPC16UC88AA as the standard boot source so engineers could load bitstreams with a single JTAG command, then iterate by reprogramming the EPC16 itself in-system. The ISP (in-system programming) interface removes the need for a stand-alone PROM programmer and accelerates lab bring-up. With 16 Mb of storage the EPC16UC88AA can hold multiple ACEX 1K bitstream revisions, allowing golden-image rollback during prototype characterization. The 88-UBGA package fits inside the standard ACEX 1K board reference layout published by Altera, eliminating rework when swapping a smaller EPC8 for the EPC16. DCLK frequencies up to the EPC16's maximum configuration rate keep ACEX 1K configuration time under one second for typical designs. Source: Altera enhanced configuration devices datasheet, ISP section.
Recommended
Networking Line-Card Boot Source
Networking line cards built on Altera FLEX 10K or APEX 20K FPGAs use the EPC16UC88AA as a discrete boot source, separating the FPGA bitstream from the line-card's main flash and simplifying firmware revision control. The dedicated DCLK/DATA handshake and JTAG ISP let network-operations teams push field updates without removing the line card from service. With 16 Mb density the EPC16 can hold the FPGA image plus a small factory-recovery image, supporting FOTA-style fallback. The 88-UBGA's 11x8 mm footprint fits inside a typical line-card BGA fan-out zone, and the 3.3V supply matches the FPGA's configuration I/O voltage for direct connection. Cascade chains of up to 8 EPC16 devices support multi-FPGA line cards. Source: Altera EPC family datasheet, cascade mode.
Recommended
Multi-FPGA Cascade Configuration
When a system board hosts more than one Altera SRAM-based FPGA, the EPC16UC88AA supports a master/slave cascade of up to 8 devices so that a single master EPC16 streams the bitstream through the slave chain, sequencing each FPGA in turn. This avoids dedicating one boot PROM per FPGA and reduces BOM cost. The 16 Mb density comfortably holds multi-FPGA golden images with compression, and the same DCLK/DATA/nCONFIG protocol extends seamlessly across the cascade. The 88-UBGA's compact footprint allows the master EPC16 to be placed near the first FPGA while still routing cleanly to subsequent slaves. Industrial users benefit from the EPC16QI100N industrial-temp sibling for harsh-edge deployments. Source: Altera Enhanced Configuration Devices datasheet, cascade chaining section.
Recommended
Legacy Avionics / Defense FPGA Board
Long-lifecycle avionics and defense platforms built around FLEX 10K and APEX 20K FPGAs use the EPC16UC88AA as a deterministic, non-volatile boot source that survives decades in the field. The part's lead-free / RoHS-compliant finish (per DigiKey listing) and 0-70 C operating envelope support ruggedized enclosures. On-chip ~35% decompression allows the bitstream to be stored compressed, reducing programming time and improving reliability over the legacy programming window. The JTAG ISP interface permits depot-level firmware updates without desoldering the PROM. For programs extending past 2030, designers often migrate to EPCQ family parts, but the EPC16UC88AA remains the in-service solution today. Source: Altera EPC family datasheet; DigiKey product listing for EPC16UC88AA.
Recommended
Recommended Products Summary
Engineering reference data for EPC16UC88AA — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPC16UC88 | EPC16QI100 | EPC16QI100N | EPC16QC100 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 88-UBGA (11x8) | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same | 88-UBGA (11x8) - same |
| Memory Size | 16 Mb (16,777,216 bits) | 16 Mb | 16 Mb | 16 Mb | 16 Mb |
| Supply Voltage | 3.0 - 3.6 V | 3.0 - 3.6 V | 3.0 - 3.6 V | 3.0 - 3.6 V | 3.0 - 3.6 V |
| On-Chip Decompression | Yes (~35%) | Yes (~35%) | Yes (~35%) | Yes (~35%) | Yes (~35%) |
| In-System Programmable | Yes (JTAG ISP) | Yes (JTAG ISP) | Yes (JTAG ISP) | Yes (JTAG ISP) | Yes (JTAG ISP) |
| Operating Temperature | 0 C to 70 C | 0 C to 70 C | -40 C to 85 C (industrial) | -40 C to 85 C (industrial) | 0 C to 70 C |
| Cascade Support | Up to 8 devices | Up to 8 devices | Up to 8 devices | Up to 8 devices | Up to 8 devices |
| Lifecycle Status | Obsolete | Obsolete | Obsolete / legacy | Obsolete / legacy | Obsolete / legacy |
Key Differentiators
- Altera-native configuration handshake with on-chip decompression (vs EPC16UC88 (same-family base code))
- Higher commercial operating temperature vs industrial QI variants (vs EPC16QI100N)
- 88-UBGA compact footprint shared across the entire EPC16 family (vs EPC16QC100 (legacy non-AA catalog code))
Design Notes
The 88-UBGA package requires microvia or sub-100-um fan-out escape routing. Place 0.1 uF decoupling capacitors within 1-2 mm of every VCC ball to suppress switching transients during the configuration handshake. A continuous ground plane on layer 2 is recommended to control return-current paths on the DCLK and DATA traces, which carry sub-100-MHz content during boot.
Route DCLK and DATA as length-matched 50-ohm microstrip traces; mismatch above 200 mil introduces setup-time violations on the target FPGA at higher DCLK rates. Keep the DCLK/DATA pair on the same PCB layer to avoid via-induced skew. Avoid routing them adjacent to high-speed memory buses; if unavoidable, insert a ground trace as a guard.
Do not connect the EPC16UC88AA's DATA pin to the FPGA's JTAG TDI - they are different signals. The EPC16's DATA output drives the FPGA's DATA0 configuration input, while JTAG uses the EPC16's dedicated TCK/TMS/TDI/TDO pins. Also verify the target FPGA's VCCIO is set to 3.3V during configuration; some FPGAs default to a different voltage that can damage the EPC16's output drivers.
Compliance Information
RoHS and lead-free confirmed via DigiKey listing for EPC16UC88AA. AEC-Q100 not applicable - this is a commercial-grade boot PROM. REACH compliance assumed by distributor listing but not independently verified.
