Intel

EPF10K10QC208-4N - FLEX 10K FPGA, 10K Gates, 208-PQFP | Intel / Altera

Name: EPF10K10QC208-4N - FLEX 10K FPGA, 10K Gates, 208-PQFP | Intel / Altera
Brand: Intel
SKU: EPF10K10QC208-4N
Price: 16.2 USD
Availability: InStock

MPN: EPF10K10QC208-4N ✗ End of Life

In Stock Ships in 1-3 business days

5 V Vdss 208-pin PQFP / 208-BFQFP Package 125 MHz Speed 6,144 Memory

From $16.2 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$32.5	$32.50
10	$28.4	$284.00
100	$22.15	$2,215.00
500	$18.6	$9,300.00
1,000	$16.2	$16,200.00

ℹ️ All prices are in USD

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EPF10K10QC208-4N Overview

The Intel / Altera EPF10K10QC208-4N is a member of the FLEX 10K family of FPGAs that delivers 10,000 usable gates with 576 logic elements, 72 LABs/CLBs, and 134 user I/Os in a 208-pin PQFP (Plastic Quad Flat Pack) package. Fabricated on a 0.42 µm CMOS SRAM-based process and operating from a single 5 V supply, the device supports system clock frequencies up to 125 MHz with the -4 speed grade, and includes 6,144 bits of embedded memory.

FLEX 10K is the first family to combine the high density of gate arrays with the programmability of FPGAs, integrating a sea-of-gates architecture called FastTrack Interconnect that delivers predictable, fixed interconnect delays regardless of routing density. The device family introduced the concept of embedded array blocks (EABs) used for memory and arithmetic functions, which became the architectural foundation for later Altera Stratix families. The EPF10K10QC208-4N is a second-source-friendly 5 V logic part that maps cleanly into industrial and legacy telecom/industrial designs.

Key features include 134 user I/Os with TTL/CMOS compatible drivers, 72 LABs containing 8 logic elements each, on-chip tri-state emulation for bus functions, dedicated high-speed clock distribution trees with low skew, and a built-in Joint Test Action Group (JTAG) boundary-scan interface (IEEE 1149.1). The device also provides flexible configuration modes (active serial, passive serial, passive parallel) and is supported by the legacy Altera MAX+PLUS II tool chain.

The architecture separates logic (LABs) from interconnect (FastTrack rows/columns), giving designers predictable timing closure on legacy 5 V designs. Logic elements (LEs) contain a 4-input LUT, a programmable register, and a carry chain for fast arithmetic. EABs provide RAM/ROM and arithmetic functions, eliminating the need for separate memory chips in small designs. Configuration is loaded from a serial EPROM or microcontroller, supporting in-system re-programmability.

Typical applications include industrial control glue logic, telecommunications line cards, legacy 5 V microcontroller/ASIC replacement, prototype ASIC emulation, and low-density DSP pre/post-processing. The wide 5 V tolerance also makes the part a popular choice for legacy avionics, factory automation, and instrumentation that has not migrated to 3.3 V.

When designing with this FPGA, ensure that all unused I/Os are properly terminated and that the JTAG chain is correctly buffered for board-level test access. The 5 V supply and PQFP package simplify PCB layout but the 208-pin PQFP has finer pitch than modern BGAs, so careful signal integrity analysis is recommended for high-speed signals.

Drop-in alternatives for EPF10K10QC208-4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF10K10QC208-4N (same form factor and footprint) — differing in Package, Family, Process Technology, Speed Grade, Configuration Method.

EPF10K10AQC208-2

Intel

Package: 208-Pin PQFP (BFQFP) 28x28 mm

Family: FLEX-10KA

Process Technology: 0.3 um CMOS SRAM