Intel

EPF8636AQC160-4N - FLEX 8000 FPGA 6K Gates 504 Cells | Intel

Name: EPF8636AQC160-4N - FLEX 8000 FPGA 6K Gates 504 Cells | Intel
Brand: Intel
SKU: EPF8636AQC160-4N
Price: 52.3 USD
Availability: InStock

MPN: EPF8636AQC160-4N ✗ End of Life

In Stock Ships in 1-3 business days

5 V Vdss 160-pin PQFP (Plastic Quad Flat Pack) Package 125 MHz Speed

From $52.3 USD / Unit

MOQ: 1 |

Price updated: 2026-09-11

Volume Pricing

Qty	Unit Price	Extended
1	$78.5	$78.50
10	$72.1	$721.00
100	$65.4	$6,540.00
500	$58.75	$29,375.00
1,000	$52.3	$52,300.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

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EPF8636AQC160-4N Overview

The Intel EPF8636AQC160-4N is a member of the legacy FLEX 8000 family of SRAM-based FPGAs, providing approximately 6,000 usable gates, 504 logic cells, and 118 user I/Os in a 160-pin PQFP package. It is fabricated on a 0.42 µm CMOS SRAM process, operates from a 5 V supply, and is rated for a commercial temperature range of 0 °C to 70 °C. The device targets glue-logic, bus-interface, and PCI-compliant system designs that need non-volatile in-system reconfigurability via an external EPROM or Altera EPC1/EPC1064/EPC1213/EPC1441 configuration device.

An FPGA (Field Programmable Gate Array) is a reprogrammable digital IC whose logic and interconnects are configured by static RAM cells. FPGAs sit within the broader programmable logic hierarchy (PLD → CPLD → FPGA) and are commonly classed as a sub-category of digital ASICs/structured ASICs. They are used wherever a custom digital function must be implemented quickly and updated without respinning silicon, and FLEX 8000 was Altera's first-generation high-density FPGA family introduced in the mid-1990s, later folded into the Intel FPGA portfolio after the 2015 Altera acquisition.

Key features of the EPF8636AQC160-4N include 504 logic elements, 118 user I/Os, embedded JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices, peripheral registers for fast setup and clock-to-output delay, full PCI Local Bus Specification compliance, and 5 V / 3.3 V I/O compatibility. Maximum toggle performance is approximately 125 MHz internally, with Fmax typically reported near 83 MHz for register-rich designs.

Architecturally, FLEX 8000 devices use continuous, SRAM-based lookup-table (LUT) logic elements arranged in Logic Array Blocks (LABs), interconnected by FastTrack continuous routing. Configuration data is loaded at power-up from an industry-standard parallel EPROM, an Altera serial configuration device, or a system controller, giving true in-circuit reconfigurability (ICR).

Typical applications include PCI bus interface bridges, peripheral glue logic in industrial controllers, legacy telecom backplane controllers, and JTAG-driven prototype boards. The 160-pin PQFP footprint and 5 V I/O make it a drop-in option for legacy designs that still require a high-density 5 V FPGA rather than a modern 3.3 V or 1.8 V device.

When designing with this device, ensure the configuration EPROM is sized for the compressed bitstream, observe 5 V VCCIO ramp sequencing, and use Altera MAX+PLUS II or Quartus for synthesis. JTAG BST pins must be reserved if boundary-scan testing is required.

This page synthesizes distributor pricing, drop-in alternatives within the FLEX 8000 family, and practical design notes not found in the original datasheet, giving engineers a single reference for sourcing and migrating legacy designs.

Drop-in alternatives for EPF8636AQC160-4N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPF8636AQC160-4N (same form factor and footprint) — differing in Package, Configuration Method, Usable Gates, Speed Grade, Logic Array Blocks (LABs).

EPF8452AQC160-3

Altera

Package: 160-pin PQFP (BQFP)

Configuration Method: SRAM, in-circuit reconfigurable

Usable Gates: 4,000