Intel

EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera

MPN: EPM9560RC208-16 ✗ End of Life

In Stock Ships in 1-3 business days

5 V Vdss 208-pin Power Quad Flat Pack (RQFP) Package 117.6 MHz Speed

From $52.4 USD / Unit

MOQ: 1 |

Price updated: 2026-09-13

Volume Pricing

Qty	Unit Price	Extended
1	$78.5	$78.50
10	$72	$720.00
100	$64.5	$6,450.00
500	$58.2	$29,100.00
1,000	$52.4	$52,400.00

ℹ️ All prices are in USD

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EPM9560RC208-16 Overview

The Intel (formerly Altera) EPM9560RC208-16 is a member of the MAX 9000 in-system programmable Complex Programmable Logic Device (CPLD) family, offering 12,000 usable gates, 560 macrocells, and a 16 ns pin-to-pin logic delay in a 208-pin Power Quad Flat Pack (RQFP) package. It is built on a 0.35 µm CMOS EEPROM process and operates from a 5 V supply, providing non-volatile, instant-on configuration that does not require an external boot PROM. The device features 416 user I/O pins, JTAG (IEEE 1149.1) boundary-scan support, and a 117.6 MHz internal fMAX for high-performance glue-logic integration.

What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks with a central interconnect fabric. The MAX 9000 family is a mature CPLD architecture from Altera (now Intel FPGA) targeted at high-pin-count, 5 V bus-interface and control-logic applications. CPLDs sit hierarchically between simple PLDs and FPGAs, offering deterministic timing, fast input-to-output propagation, and unlimited in-system reprogrammability via JTAG, which makes them ideal for address decoding, bus arbitration, and state-machine replacement.

Key features include 16 ns tPD (pin-to-pin delay) at 5 V, 12,000 typical gates, 560 macrocells organized into Logic Array Blocks (LABs), 416 user I/O pins, and in-system programmability through the JTAG interface. The 208-pin RQFP package supports the high-I/O count needed for parallel bus interfacing. Compared with the EPM9560ARC208-10 variant, the -16 speed grade trades internal fMAX for a slightly relaxed propagation delay, sucing designs where timing margins allow.

Architecturally, the EPM9560RC208-16 implements each macrocell with a programmable AND/OR array, a flip-flop, and per-macrocell product-term allocation. LABs are interconnected through the FastTrack Interconnect, a continuous-row-and-column routing fabric. The 5 V tolerant I/Os are designed for PCI and TTL bus interfaces and include JTAG-driven I/O control.

Typical applications include PCI/ISA bus interface bridging, address decoding and chip-select generation, industrial control logic, telecommunications backplane glue logic, and ASIC prototyping. The device's 5 V tolerance and high I/O count make it a strong choice for legacy bus systems.

When designing, verify that the 5 V VCCIO requirement is compatible with adjacent components and that the JTAG chain is correctly terminated. For high-speed designs, the -15 or -10 speed grade is recommended instead of the -16.

This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC208-16 not collected in the manufacturer datasheet.

Drop-in alternatives for EPM9560RC208-16 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EPM9560RC208-16 (same form factor and footprint) — differing in Package, User I/O Pins, Usable Gates, Pin-to-Pin Delay (tPD), Propagation Delay (tPD).

EPM9480RC208-15

Intel

Package: RQFP-208

User I/O Pins: 153

Usable Gates: 10,000 gates