IQE008N03LM5CGSCATMA1 - 30V 0.85mOhm Dual N-MOSFET | Infineon
MPN: IQE008N03LM5CGSCATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.45 | $3.45 |
| 10 | $3.12 | $31.20 |
| 100 | $2.74 | $274.00 |
| 500 | $2.39 | $1,195.00 |
| 1,000 | $2.1 | $2,100.00 |
IQE008N03LM5CGSCATMA1 Overview
A power MOSFET is a voltage-controlled semiconductor switch used to efficiently route or regulate current in power-conversion circuits. The OptiMOS 5 family represents Infineon's fifth-generation trench MOSFET technology optimized for low on-resistance per unit area, low gate charge, and low figure-of-merit (FOM). Within the broader hierarchy, a MOSFET is a discrete semiconductor -> power transistor -> voltage-controlled switch -> building block of switched-mode power supplies (SMPS), motor drives, and battery protection. The dual MOSFET array form factor further reduces parasitic inductance between the two FETs by sharing a common package.
Key features include a maximum drain-source voltage of 30 V, a continuous drain current of 252 A per channel at the case-temperature-limited rating, an ultra-low maximum RDS(on) of 0.85 mOhm at VGS=10 V, and a logic-level gate threshold that supports standard 10 V and potentially lower drive voltages. The PG-WHTFN-9 package features top-side and bottom-side thermal pads (dual cooling), enabling direct heat extraction from both PCB surfaces for high-density designs such as server VRMs and telecom bricks.
Technically, the IQE008N03LM5 uses Infineon's latest-generation silicon trench process, achieving the 0.85 mOhm rating in a compact package without sacrificing avalanche ruggedness. The dual-die construction balances the two MOSFETs symmetrically so the array can be used in high-side/low-side roles. Compared with discrete MOSFETs of similar rating, the integrated array reduces loop inductance between the two switches and simplifies PCB layout.
Typical applications include synchronous rectification in 12 V and 24 V SMPS, server and telecom DC-DC converters, hot-swap and OR-ing controllers, motor drive half-bridges, and battery management systems (BMS) where very low conduction loss is required at high currents.
When designing with this part, ensure the gate driver can source/sink the Qg charge and that adequate thermal vias connect both the top and bottom exposed pads to inner copper planes. The 30 V absolute maximum demands strict layout discipline when used near 24 V input rails with transients.
This page synthesizes distributor pricing, parametric data from the Infineon datasheet, drop-in alternatives in the same PG-WHTFN-9 footprint, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for IQE008N03LM5CGSCATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IQE008N03LM5CGSCATMA1 (same form factor and footprint) — differing in Package, Technology, Gate Threshold Voltage (VGS(th)), Drain-Source Voltage (VDS), Operating Temperature Range.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IQE008N03LM5SCATMA1
✅ Drop-In✓ In Stock
$1.18 / Unit
View Datasheet →IQE012N03LM5CGATMA1
✅ Drop-In✓ In Stock
$1.38 / Unit
View Datasheet →IQEH50NE2LM7UCGSCATMA1
✅ Drop-In✓ In Stock
$1.78 / Unit
View Datasheet →IQE220N15NM5CGSCATMA1
✅ Drop-In✓ In Stock
$2.18 / Unit
View Datasheet →BSC076N04NDATMA1
✅ Drop-In✓ In Stock
$0.82 / Unit
View Datasheet →IPC50N04S5L5R5ATMA1
✅ Drop-In✓ In Stock
$0.36 / Unit
View Datasheet →IQE008N03LM5CGSCATMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Product Family | OptiMOS 5 |
| Configuration | Dual N-Channel MOSFET Array |
| Drain-Source Voltage (VDS) Max | 30 V |
| Continuous Drain Current (ID) Max | 252 A (per channel, case-temperature limited) |
| On-Resistance (RDS(on)) Max | 0.85 mOhm at VGS = 10 V |
| Gate Threshold Voltage (VGS(th)) | 2 V (typ) |
| Operating Temperature Range | -55C to +150C (junction) |
| Package | PG-WHTFN-9 (WHTFN) |
| Mounting Type | Surface Mount (top + bottom cooling) |
| Technology | Trench MOSFET (OptiMOS 5) |
| Polarity | N-Channel |
| Number of Pins | 9 (WHTFN with exposed thermal pads) |
| MSL Level | 1 (per JEDEC J-STD-020, typical for Infineon Power-SMD packages) |
| RoHS Status | Compliant |
| Halogen-Free | Yes (Infineon standard for OptiMOS 5) |
IQE008N03LM5CGSCATMA1 Pin Configuration
| Pin 1 | G1 — Gate of MOSFET 1 (high-side or low-side channel) |
| Pin 2 | S1 — Source of MOSFET 1 |
| Pin 3 | S1 — Source of MOSFET 1 (continued) |
| Pin 4 | D — Common Drain connection |
| Pin 5 | D — Common Drain connection (continued) |
| Pin 6 | D — Common Drain connection (continued) |
| Pin 7 | S2 — Source of MOSFET 2 |
| Pin 8 | S2 — Source of MOSFET 2 (continued) |
| Pin 9 | G2 — Gate of MOSFET 2 |
Safe Operating Area - IQE008N03LM5CGSCATMA1
Typical Applications
IQE008N03LM5CGSCATMA1 is suitable for 6 applications: Synchronous Rectification in 12V / 24V SMPS, Server and Telecom Point-of-Load Converters, Hot-Swap and OR-ing Controllers, High-Current Half-Bridge Motor Drives, Battery Management System (BMS) Protection FETs, Telecom Brick DC-DC Converters.
Synchronous Rectification in 12V / 24V SMPS
The IQE008N03LM5CGSCATMA1's 30 V VDS and 0.85 mOhm RDS(on) make it ideal for synchronous rectification in 12 V and 24 V switched-mode power supplies. In a typical 12 V to 1 V buck converter the low-side FET sees the full load current during the freewheel phase - at 80 A load, the IQE008N03LM5 dissipates only 0.85 mOhm * 80 A^2 * 50% duty = 2.7 W vs much higher losses with discrete FETs. The dual-die PG-WHTFN-9 package halves the high-side/low-side loop inductance compared with two discrete SO-8 parts, reducing switching loss and dv/dt-induced ringing on the switch node.
Recommended
Server and Telecom Point-of-Load Converters
In 48 V-to-PoL intermediate bus converters and direct-conversion VRM topologies the IQE008N03LM5CGSCATMA1's 252 A current rating and PG-WHTFN-9 dual-cooling package address the thermal density challenge of server boards. The top and bottom exposed pads spread heat to both PCB surfaces, allowing a 6-layer server PCB to dissipate 5-7 W per channel without a heatsink. RDS(on) of 0.85 mOhm at 10 V drive keeps conduction loss under 2% even at 100 A continuous load, critical for meeting 80+ Titanium efficiency targets in hyperscale datacenters.
Recommended
Hot-Swap and OR-ing Controllers
The IQE008N03LM5CGSCATMA1 is well-suited as the main pass element in -48 V / +12 V OR-ing and hot-swap controllers where two redundant power sources feed a common load. Its 0.85 mOhm RDS(on) at 252 A limits steady-state voltage drop to about 21 mV, minimizing dissipation in the OR-ing path. The 30 V VDS provides comfortable headroom over a 12 V rail, and the dual-die package simplifies the layout by combining two switches into one component. Use a dedicated OR-ing controller IC upstream to handle fast turn-off during reverse-current faults.
Recommended
High-Current Half-Bridge Motor Drives
Brushless DC (BLDC) and permanent-magnet synchronous motor (PMSM) drives in 24 V battery-powered applications can use the IQE008N03LM5CGSCATMA1 as the high-side / low-side half-bridge switches. At 50 A continuous phase current, conduction loss is approximately 2.1 W per switch, and the 30 V VDS comfortably handles the inductive kick of a 24 V motor with margin for regen transients. The PG-WHTFN-9 dual-cooling package enables direct PCB cooling without an aluminum heatsink, reducing assembly cost and height.
Recommended
Battery Management System (BMS) Protection FETs
In 12 V to 24 V battery packs the IQE008N03LM5CGSCATMA1 can serve as the high-side or low-side disconnect FET for short-circuit and over-current protection. The 30 V VDS and 252 A current rating exceed the continuous discharge rating of typical Li-ion packs, and the 0.85 mOhm RDS(on) introduces less than 1% loss during normal operation - critical for applications such as e-mobility and stationary storage. The PG-WHTFN-9 dual-cooling design spreads the I^2*R heat during a fault event, reducing the chance of thermal runaway before the protection circuit trips.
Recommended
Telecom Brick DC-DC Converters
The IQE008N03LM5CGSCATMA1 can be used as the primary-side synchronous rectifier in 24 V or 48 V-to-isolated 12 V telecom bricks. Its 30 V VDS provides a margin over the rectified 24 V bus (typically 36 V peak after PFC) and the 0.85 mOhm RDS(on) at 252 A limits full-load efficiency loss to under 1.5% for the rectification stage. Combined with the dual-cooling PG-WHTFN-9 package, this enables telecom bricks in 1/4-brick and 1/8-brick form factors with passive cooling up to 300 W output.
Recommended
Recommended Products Summary
Engineering reference data for IQE008N03LM5CGSCATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IQE008N03LM5SCATMA1 | IQE012N03LM5CGATMA1 | IQEH50NE2LM7UCGSCATMA1 | BSC076N04NDATMA1 |
|---|---|---|---|---|---|
| Package | PG-WHTFN-9 (WHTFN) | PG-WHTFN-9 (WHTFN) - same | PG-WHTFN-9 (WHTFN) - same | PG-WHTFN-9 (WHTFN) - same | PG-WHTFN-9 (WHTFN) - same |
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Drain-Source Voltage (VDS) Max | 30 V | 30 V | 30 V | 50 V | 40 V |
| Technology Generation | OptiMOS 5 | OptiMOS 5 | OptiMOS 5 | OptiMOS 7 | OptiMOS 5 |
| Dual-Cooling Package | Yes (top + bottom pads) | Yes | Yes | Yes | Yes |
Key Differentiators
- Ultra-low 0.85 mOhm RDS(on) in dual-die PG-WHTFN-9 (vs Discrete 30 V MOSFETs in SO-8 (typical RDS(on) 2-3 mOhm))
- Dual-side cooling via top + bottom exposed pads (vs Single-bottom-pad packages like SO-8 or DFN-8)
- Latest OptiMOS 5 trench technology with 252 A continuous rating (vs Older OptiMOS 3/4 generation parts in the same package)
Design Notes
Estimated: at VGS=10V, continuous 100A load per channel, the IQE008N03LM5CGSCATMA1 dissipates approximately P = I^2 * RDS(on) = 100^2 * 0.85 mOhm = 8.5 W per channel. On a 40 mm x 40 mm FR4 PCB with 6 cm^2 copper per side per the Infineon datasheet condition, junction-to-ambient thermal resistance is approximately 40 C/W, giving a 340 C rise over ambient - so a heatsink or substantial copper pour is mandatory for high-current operation. The PG-WHTFN-9 dual-cooling design pulls heat through BOTH top and bottom pads - be sure to place thermal vias in BOTH pad areas, not just the bottom pad as is common with SO-8 footprints.
The PG-WHTFN-9 source pins act as both electrical connection AND thermal path. Place a continuous copper pour directly under the source pins with multiple thermal vias (0.3 mm drill, 1 mm pitch) to the inner plane. Keep the high-side/low-side switch-node copper minimal (no wide pours) to reduce parasitic capacitance and dv/dt coupling. Gate-drive traces should be 0.2 mm or wider and routed away from the switch node to avoid false triggering at high dV/dt (the typical OptiMOS 5 dV/dt rating is 50 V/ns or higher - verify in the datasheet).
Do NOT use the 30 V VDS rating at full margin - the actual repetitive avalanche energy from inductive kickback can quickly exceed the datasheet EAS rating if no snubber or TVS clamp is used. For 24 V input rails with no transformer isolation, add a 33 V or 36 V TVS across the drain-source to absorb transients. Also, do not parallel the two internal MOSFETs externally without accounting for the shared drain pad - the source pins are bonded to the same internal lead frame for each FET, so the high-side and low-side usage is the natural configuration.
Compliance Information
RoHS and REACH compliant per Infineon OptiMOS 5 product family standards. Not AEC-Q100 qualified; automotive applications require the IQE automotive-grade variant. Lead-free and halogen-free per Infineon's published material declarations.
