PCF85063AT/AY - RTC, I2C 400kHz, SOIC-8 | NXP Semiconductors
MPN: PCF85063AT/AY β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.49 | $0.49 |
| 10 | $0.46 | $4.60 |
| 100 | $0.42 | $42.00 |
| 500 | $0.38 | $190.00 |
| 1,000 | $0.34 | $340.00 |
PCF85063AT/AY Overview
A Real-Time Clock (RTC) is a timekeeping IC that tracks seconds, minutes, hours, days, weekdays, months, and years while the main processor sleeps or is powered down. Within the power-management and clock/timing IC hierarchy, an RTC sits alongside microcontroller supervisory functions and is typically paired with a 32.768 kHz crystal and a backup coin cell so that time-of-day data survives main-power loss.
Key features of the PCF85063AT/AY include year 2000-compliant calendar with automatic leap-year correction, an alarm function with interrupt output, an offset register that allows fine-tuning of the clock for crystal-frequency correction, and a 32.768 kHz reference optimized for low power consumption. The device communicates over a two-line bidirectional I2C-bus with a maximum data rate of 400 kbit/s, and the register address increments automatically after each written or read data byte.
The CMOS architecture keeps standby current extremely low, which directly extends backup-battery life in metering and battery-powered designs. The offset register enables software calibration, compensating for crystal tolerance without an external trimming capacitor - a meaningful advantage for high-volume production where per-unit crystal spread would otherwise require manual adjustment.
Typical applications include smart meters and utility metering, battery-powered portable and wearable devices, industrial controllers that must retain time across power cycles, and automotive-adjacent systems via the AEC-Q100-qualified PCF85063AT/AAZ variant.
When designing with this device, place the 32.768 kHz crystal as close as possible to the OSCI/OSCO pins, use a guaranteed 32.768 kHz crystal with the load capacitance specified in the NXP datasheet, and route the I2C SDA/SCL lines away from noisy switching nodes.
This page synthesizes distributor pricing, drop-in alternatives, pinout, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for PCF85063AT/AY β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
PCF85063AT/AAZ
β Drop-Inπ Reference alternative (not in catalog)
PCF85063AT/A
β Drop-Inπ Reference alternative (not in catalog)
PCF85063AT/AYZ
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
PCF85063AT/AY Specifications
| Product Type | Real-Time Clock (RTC) and calendar with alarm |
| Interface | I2C-bus, two-line bidirectional serial |
| Maximum I2C Data Rate | 400 kbit/s |
| Crystal Frequency | 32.768 kHz |
| Calendar Functions | Seconds, minutes, hours, days, weekdays, months, years, alarm |
| Offset Register | Yes - fine-tuning of the clock |
| Alarm Function | Yes, with interrupt output |
| Package | SOIC-8 (SO8), 0.154 inch, 3.90 mm width |
| Mounting Type | Surface Mount |
| Technology | CMOS |
| Automatic Register Increment | Yes, after each written or read data byte |
| RoHS Status | Compliant |
| Lifecycle Status | Active (per NXP product page) |
PCF85063AT/AY Pin Configuration
| Pin 1 | OSCI β Oscillator input - 32.768 kHz crystal input |
| Pin 2 | VSS β Ground supply |
| Pin 3 | INT β Interrupt output (alarm) |
| Pin 4 | CLKOUT β Clock output |
| Pin 5 | SDA β I2C-bus serial data |
| Pin 6 | SCL β I2C-bus serial clock |
| Pin 7 | VDD β Positive supply |
| Pin 8 | OSCO β Oscillator output - 32.768 kHz crystal output |
Typical Applications
PCF85063AT/AY is suitable for 6 applications: Smart Meters and Utility Metering, Battery-Powered Portable and Wearable Devices, Industrial Controllers and PLC I/O Modules, Data Loggers and Security Recorders, POS, Billing and Payment Terminals, Automotive Subsystems (via /AAZ variant).
Smart Meters and Utility Metering
The PCF85063AT/AY fits smart electricity, gas, and water meters where time-of-use tariffing and load-profile logging require an accurate, battery-backed calendar. Its CMOS design is optimized for low power consumption, so a small backup cell can maintain timekeeping for years during grid outages. The 400 kbit/s I2C interface connects directly to the metering MCU without burdening the bus, and the alarm with interrupt output can wake the processor for scheduled reading or reporting events. The offset register allows fine-tuning of the clock, letting production firmware compensate for per-unit crystal tolerance and keeping the tariff clock within regulatory drift limits without manual trimming.
Recommended
Battery-Powered Portable and Wearable Devices
In wearables, medical patches, and portable instruments, the PCF85063AT/AY provides time-of-day and alarm capability in a compact SOIC-8 (3.90 mm width) footprint while the main SoC sleeps. Because the PCF85063A is a CMOS RTC optimized for low power consumption, it keeps the average system current dominated by the radio and display rather than timekeeping. The 400 kbit/s I2C-bus interface allows fast burst reads of the time registers on wake-up, and the INT output supports wake alarms without polling. The offset register permits firmware-based crystal calibration, which is valuable where a tuning-fork crystal's tolerance would otherwise accumulate visible clock drift over weeks of battery operation.
Recommended
Industrial Controllers and PLC I/O Modules
Industrial controllers must timestamp events, schedule maintenance actions, and retain correct time across power cycles and brownouts. The PCF85063AT/AY provides a full seconds-to-years calendar with leap-year handling and an alarm interrupt, communicating with the controller CPU over the standard 400 kbit/s I2C bus. Its register address increments automatically after each data byte, so a complete time-stamp read is a single bus transaction, minimizing CPU overhead in scan-cycle-critical firmware. For installations exposed to wide temperature ranges or requiring automotive-grade sourcing, the pin-compatible AEC-Q100 PCF85063AT/AAZ variant offers the same footprint and register map for qualification continuity.
Recommended
Data Loggers and Security Recorders
Event and environmental data loggers rely on the PCF85063AT/AY to give every recorded sample a trustworthy timestamp that survives power interruption. The RTC's low-power CMOS core keeps the backup-battery budget small, while the alarm function with interrupt output triggers periodic logging wake-ups without host polling over the 400 kbit/s I2C bus. The offset register enables fine clock tuning, so logger drift over a multi-month deployment stays within the accuracy stated in the analysis report. Designers should place the 32.768 kHz crystal close to OSCI/OSCO and keep I2C traces short to preserve timekeeping accuracy in electrically noisy logging environments.
Recommended
POS, Billing and Payment Terminals
Point-of-sale terminals and billing equipment need tamper-resistant, continuous timekeeping for receipts, audit logs, and transaction sequencing. The PCF85063AT/AY provides a year-2000-compliant calendar with automatic leap-year correction and an alarm with interrupt output, all accessible over a standard 400 kbit/s I2C bus from the terminal's application processor. Its compact SOIC-8 (3.90 mm) surface-mount package fits dense terminal PCBs, and its low power consumption allows a coin-cell backup to maintain the clock through power failures. The offset register supports firmware calibration during manufacturing, avoiding per-unit trimming capacitors in high-volume terminal production.
Recommended
Automotive Subsystems (via /AAZ variant)
Body controllers, gateway modules, and telematics units in vehicles require qualified timekeeping for event logging and scheduled functions. While this /AY part targets industrial and consumer builds, the pin-to-pin compatible PCF85063AT/AAZ carries AEC-Q100 qualification on the same SO8 footprint and identical register map, so a single PCB layout can serve both markets. The 400 kbit/s I2C interface connects the RTC to the automotive MCU, the alarm INT output supports scheduled wake-up from low-power modes, and the offset register allows firmware trimming to compensate crystal tolerance over the vehicle's temperature range. Verify supply-voltage behavior during cranking transients per the NXP datasheet.
Recommended
Recommended Products Summary
Engineering reference data for PCF85063AT/AY β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | PCF85063AT/AAZ | PCF85063AT/A | PCF85063AT/AYZ |
|---|---|---|---|---|
| Package | SOIC-8 (SO8, 3.90 mm width) | SOIC-8 (SO8) - same | SOIC-8 (SO8) - same | SOIC-8 (SO8) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Interface | I2C, max 400 kbit/s | I2C, max 400 kbit/s | I2C, max 400 kbit/s | I2C, max 400 kbit/s |
| Alarm with Interrupt | Yes (INT output) | Yes (INT output) | Yes (INT output) | Yes (INT output) |
| Offset Register (clock fine-tuning) | Yes | Yes | Yes | Yes |
| AEC-Q100 Qualification | No (industrial/consumer grade) | Yes (automotive grade) | No | No |
| Crystal Frequency | 32.768 kHz | 32.768 kHz | 32.768 kHz | 32.768 kHz |
Key Differentiators
- Offset register for software crystal calibration (vs PCF8583T/5)
- Drop-in automotive-grade path on the same footprint (vs PCF85063AT/AAZ)
- Very low power CMOS timekeeping in a compact SO8 (vs PCF8523)
Design Notes
Place the 32.768 kHz tuning-fork crystal as close as possible to the OSCI (pin 1) and OSCO (pin 8) pins, with short, direct traces and a guard ring tied to VSS. Keep the crystal traces away from the I2C SDA/SCL lines and any switching-regulator nodes, since capacitive coupling into the oscillator can pull the 32.768 kHz frequency and accumulate time drift. Use a crystal whose load capacitance matches the value specified in the NXP PCF85063A datasheet rather than relying on stray board capacitance alone.
Do not substitute other NXP RTCs (PCF8523, PCF8583) without a register-map review - their pin assignments and register behavior differ from the PCF85063A even where packages look similar. When moving between /AY and /AAZ order codes, confirm the suffix definition in the NXP ordering information. Also remember the I2C bus requires pull-up resistors on SDA and SCL; their value sets the rise time at the 400 kbit/s maximum data rate, so over-sized pull-ups will cause bus timeouts.
For battery-backup designs, budget the backup cell around the PCF85063A's timekeeping current from the NXP datasheet electrical characteristics table plus the leakage of the crystal and any divider resistors. Use the offset register for software calibration instead of a trimming capacitor: firmware calibration removes a manual production step and compensates per-unit crystal tolerance. Ensure VDD sequencing is benign - the I2C pins should not be driven high while VDD is absent, or parasitic powering through the ESD structures can drain the backup cell.
The 400 kbit/s I2C interface is Fast-mode tolerant, but long bus runs or heavy loading on SDA/SCL will violate rise-time limits. Keep bus capacitance within the I2C specification (typically with pull-ups sized for the measured bus capacitance), and consider an open-drain buffer such as the SN74LVC1G07 for branched or heavily loaded buses. Route the INT output away from the crystal area as it toggles asynchronously and can couple glitches into the oscillator.
Compliance Information
NXP product page lists PCF85063AT as Active. RoHS/lead-free per standard NXP product offering; REACH, halogen-free, and conflict-minerals status not stated in the provided data. The /AAZ suffix variant is the AEC-Q100 automotive-qualified family member.
