ESP32-P4NRW32X - Dual-Core RISC-V HMI MCU 32MB PSRAM | Espressif
MPN: ESP32-P4NRW32X ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.9 | $4.90 |
| 10 | $4.45 | $44.50 |
| 100 | $4.05 | $405.00 |
| 500 | $3.7 | $1,850.00 |
| 1,000 | $3.35 | $3,350.00 |
ESP32-P4NRW32X Overview
A microcontroller (MCU) is a single integrated circuit that combines a processor core, memory, and programmable peripherals into one chip, sitting at the heart of the embedded systems hierarchy: SoC -> microcontroller -> embedded system. The ESP32-P4 is Espressif's flagship application-class MCU, positioned above the ESP32-S3 for compute-intensive embedded workloads.
Key features include the HP/LP dual-system architecture that lets the LP core handle sleep-state housekeeping while the HP cores run demanding workloads, 32 MB of in-package PSRAM (the NRW32 variant) supporting large frame buffers, powerful image and voice processing capability, and rich HMI-oriented peripherals. Unlike most ESP32 family members, the ESP32-P4 focuses purely on compute; wireless connectivity is added externally via companion chips such as the ESP32-C6.
Technically, the HP system contains the dual-core RISC-V processor with AI instruction extensions, an advanced memory subsystem, and integrated high-speed peripherals, while the LP system contains the single-core RISC-V low-power microprocessor. This split allows always-on voice wake-word detection or sensor polling at minimal power, waking the HP cores only when needed.
Typical applications include rich Human-Machine Interfaces (HMI) with touch displays, edge computing nodes, image and camera processing pipelines, and voice processing endpoints. The large in-package PSRAM directly supports display frame buffers and AI model working sets without external memory routing.
Design consideration: Espressif recommends the v3-or-later reference schematic for new designs and at least a 4-layer PCB for the 10 x 10 mm QFN-104 footprint; strapping pins must be reviewed against the ESP32-P4 datasheet before layout is frozen.
This page synthesizes distributor pricing, drop-in alternatives, package guidance, and design notes not found in the manufacturer datasheet.
Drop-in alternatives for ESP32-P4NRW32X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ESP32-P4NRW32X (same form factor and footprint) — differing in Core (HP System), In-Package PSRAM, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ESP32-P4NRW16X
✅ Drop-In✓ In Stock
$3.2 / Unit
View Datasheet →ESP32-P4NRW32X Maximum Ratings & Electrical Characteristics
| Core (HP System) | RISC-V 32-bit dual-core high-performance microprocessor with AI instruction extensions |
| Core (LP System) | RISC-V single-core low-power microprocessor |
| Architecture | HP (High Performance) system + LP (Low Power) system |
| In-Package PSRAM | 32 MB |
| Package | QFN-104, 10 x 10 mm |
| Key Capabilities | Image processing, voice processing, rich HMI, edge computing |
| Wireless | None on-chip (use external companion such as ESP32-C6) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
ESP32-P4NRW32X qfn-104, 10 x 10 mm Pin Configuration Guide
Pin configuration for ESP32-P4NRW32X (qfn-104, 10 x 10 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for ESP32-P4NRW32X.
Refer to the datasheet for full pin configuration.
Typical Applications
ESP32-P4NRW32X is suitable for 6 applications: Rich HMI Touch Displays, Edge Computing and AI Inference, Camera and Image Processing, Voice Processing Endpoints, Industrial Automation Panels, Smart Home Controllers.
Rich HMI Touch Displays
The ESP32-P4NRW32X fits rich Human-Machine Interface applications because its dual-core RISC-V HP processor with AI instruction extensions and 32 MB of in-package PSRAM can hold multi-layer display frame buffers locally, while the high-speed integrated peripherals drive modern touch panels. In a typical design, the HP cores run the GUI framework and rendering pipeline while the LP coprocessor keeps the touch controller and backlight logic alive in light-sleep, waking the HP system only on user interaction to cut average power. The 32 MB PSRAM variant is preferred over the 16 MB ESP32-P4NRW16X when animations, rotation, or double buffering would otherwise exhaust memory. Espressif recommends the v3-or-later reference schematic and a 4-layer PCB for signal integrity on this QFN-104 footprint.
Recommended
Edge Computing and AI Inference
For edge computing nodes, the ESP32-P4NRW32X offers a dual-core RISC-V CPU with AI (vector) instruction extensions that accelerate quantized neural network inference, and its 32 MB of in-package PSRAM comfortably holds model weights and activation buffers without external memory. The advanced memory subsystem keeps the HP cores fed, while the LP coprocessor handles sensor polling and event detection at microamp-scale power between inference sessions. Typical deployments include anomaly detection on industrial equipment, keyword spotting, and smart-building gateways. Because the chip has no on-chip radio, pair it with an ESP32-C6 companion for cloud connectivity. The QFN-104 10 x 10 mm package keeps board area compact even with the companion and power tree included on a 4-layer stackup.
Recommended
Camera and Image Processing
Image pipelines are memory-hungry, and this is where the ESP32-P4NRW32X's 32 MB of in-package PSRAM directly enables the application: raw camera frames at QVGA-to-HD resolutions fit on-chip, avoiding the routing complexity and signal-integrity risk of external PSRAM. The HP system's high-speed peripherals interface camera sensors, while the dual-core RISC-V HP processor with AI extensions performs format conversion, resizing, and on-device detection or classification. The LP system can monitor a PIR sensor and wake the HP cores only when motion is detected, dramatically cutting standby power in battery-backed cameras. Designers should allocate PSRAM carefully - a single VGA RGB565 frame consumes about 1.2 MB, leaving ample room for double or triple buffering within the 32 MB budget.
Recommended
Voice Processing Endpoints
Voice front-ends benefit from the ESP32-P4NRW32X's architecture split: the LP coprocessor runs the always-on wake-word detector at minimal power, then wakes the dual-core HP system for full speech command recognition, audio codecs, and network transmission. The 32 MB in-package PSRAM holds acoustic models, audio ring buffers, and echo-cancellation working sets simultaneously - a budget that the 16 MB ESP32-P4NRW16X may exhaust in far-field multi-microphone designs. The HP system's high-speed integrated peripherals include the audio interfaces needed for I2S microphone arrays. Note that network audio streaming requires an external wireless companion such as the ESP32-C6, keeping RF certification decoupled from the voice compute board.
Recommended
Industrial Automation Panels
Industrial HMI panels and machine-interface controllers use the ESP32-P4NRW32X to combine a responsive graphical display, fieldbus communication, and local analytics in one MCU. The dual-core HP system partitions rendering from control logic, so touch responsiveness does not suffer when protocol stacks run concurrently, while the LP coprocessor maintains watchdog and sensor monitoring through deep-sleep idle periods. The 32 MB PSRAM supports screen composition, data-logging buffers, and protocol state machines without external memory. For environments demanding wide operating temperature or functional safety, verify the specific chip revision and qualification data against the ESP32-P4 Series Errata before committing. Espressif's v3-or-later reference schematic and 4-layer PCB recommendation apply directly to industrial EMI conditions.
Recommended
Smart Home Controllers
Smart-home hubs and scene controllers leverage the ESP32-P4NRW32X's compute headroom to run a local UI, protocol translation, and automation rules simultaneously. Pairing the P4's dual-core RISC-V HP system with an ESP32-C6 companion yields Thread, Zigbee (802.15.4), Wi-Fi, and BLE connectivity alongside strong local processing - a combination neither chip delivers alone. The 32 MB of in-package PSRAM accommodates device tables, UI assets, and over-the-air update staging buffers. In battery-conscious wall-mounted designs, the LP coprocessor holds the mesh in low-power mode and wakes the HP cores on touch or scheduled events. Layout the QFN-104 with Espressif's recommended 4-layer stack and v3 reference schematic to keep the high-speed digital domain clean.
Recommended
Recommended Products Summary
Engineering reference data for ESP32-P4NRW32X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ESP32-P4NRW16X |
|---|---|---|
| Package | QFN-104 (10 x 10 mm) | QFN-104 (10 x 10 mm) - same |
| Brand | Espressif Systems | Espressif Systems |
| HP CPU | Dual-core RISC-V 32-bit with AI extensions | Dual-core RISC-V 32-bit with AI extensions |
| LP Coprocessor | Single-core RISC-V low-power | Single-core RISC-V low-power |
| In-Package PSRAM | 32 MB | 16 MB |
| Wireless | None on-chip | None on-chip |
| RoHS | Compliant | Compliant |
| Drop-in Compatible | Yes (mutual) | Yes - same footprint, verify PSRAM budget |
Key Differentiators
- Double the in-package PSRAM (vs ESP32-P4NRW16X)
- HP + LP dual-system architecture (vs ESP32-S3)
- Decoupled RF certification (vs ESP32-S3)
Design Notes
Espressif explicitly recommends at least a 4-layer PCB for the ESP32-P4 QFN-104 (10 x 10 mm) footprint, per the esp32-p4-design-resources community reference. Use a dedicated internal ground plane, stitch the exposed pad to ground with a via array, and follow Espressif's v3-or-later reference schematic for new designs. The 104 fine-pitch balls include high-speed interfaces whose signal integrity depends directly on controlled-impedance routing and solid return paths.
The ESP32-P4 series ships multiple chip revisions under the same part number, as stated in the datasheet's chip revision section. Verify the revision on received units against the ESP32-P4 Series SoC Errata and confirm your ESP-IDF release supports it before mass production. Additionally, strapping pins are highlighted by pin name in the datasheet - review their reset-time configurations before finalizing pull-up/pull-down networks, or boot failures will appear intermittently.
The ESP32-P4 has no on-chip radio, but if you pair it with an ESP32-C6 companion for wireless, budget the RF peak current separately and provide independent decoupling for each supply domain. Keep the LP system's supply rail alive in deep sleep so the coprocessor can wake the HP cores; an inadvertent regulator shutdown of the LP domain will make the system unrecoverable without a hard reset. Esimated: allow margin on the HP rail for dual-core peak loading during AI inference.
Compliance Information
RoHS compliance confirmed via JLCPCB part listing (marked ROHS). REACH, halogen-free, and conflict-minerals status not found in verified web data - request declarations from Espressif.
