10AX090S1F45I1SG - Arria 10 GX 900K LE FPGA | Intel/Altera
MPN: 10AX090S1F45I1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4850 | $4,850.00 |
| 10 | $4650 | $46,500.00 |
| 100 | $4350 | $435,000.00 |
| 500 | $4100 | $2,050,000.00 |
| 1,000 | $3890 | $3,890,000.00 |
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View Datasheet →10AX090S1F45I1SG Maximum Ratings & Electrical Characteristics
| Product Family | Arria 10 GX |
| Logic Elements | 900,000 |
| Embedded Memory (bits) | 59,234,304 |
| DSP Blocks | Variable-precision, hard IEEE 754 single-precision floating point |
| Maximum User I/Os | 624 |
| Maximum Transceiver Data Rate | 12.5 Gbps |
| Hard Memory Controller | DDR4/DDR3/QDR-IV (per Hard Memory Controller IP) |
| Hard PCIe Gen3 IP | Yes |
| Process Node | 20nm |
| Core Voltage | 0.9 V |
| Package | 1932-ball FCBGA (F45, 45mm) |
| Temperature Grade | Industrial (I1: -40C to +100C) |
| Ordering Suffix | SG |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AX090S1F45I1SG 1932-ball fcbga (f45, 45mm) Pin Configuration Guide
Complete pinout information for 10AX090S1F45I1SG (1932-ball fcbga (f45, 45mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090S1F45I1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090S1F45I1SG is suitable for 6 applications: 100G Optical Transport Line Cards, Wireless Fronthaul / Backhaul (CPRI / OBSAI), Military Radar and Electronic Warfare, Broadcast Video Processing / Studio Infrastructure, High-Performance Computing / Hardware Accelerator, Medical Imaging and Diagnostic Equipment.
100G Optical Transport Line Cards
The 10AX090S1F45I1SG's 12.5 Gbps GX transceivers and hard PCIe Gen3 IP block make it well suited for 100G Ethernet line cards using CAUI-10 (10x10G) or CAUI-4 (4x25G via gearboxing external PHY) architectures. In a typical design the FPGA sits between the QSFP28 cage and the switch ASIC, implementing OTN framer/mapper, MAC, and statistics offload. The 900K logic elements and 59 Mb embedded memory allow full OTU4 framing without external memory pressure. Power consumption is materially lower than a Stratix 10 GT, helping meet CFP/CFP2 thermal envelopes.
Recommended
Wireless Fronthaul / Backhaul (CPRI / OBSAI)
The 10AX090S1F45I1SG's integrated 12.5 Gbps transceivers are ideal for CPRI rates up to option 7 (9.830 Gbps) and OBSAI RP3, supporting 4G LTE and 5G NR fronthaul links between baseband units and remote radio heads. The hard floating-point DSP blocks accelerate FFT/iFFT and channelization, while DDR4 hard memory controllers feed baseband sample streams without consuming fabric logic. With 624 user I/Os it provides ample margin for backplane GPIO, JTAG, and board management while keeping the bill of materials low.
Recommended
Military Radar and Electronic Warfare
Military radar and EW systems require thousands of DSP taps, deterministic latency, and tight temperature-grade control. The 10AX090S1F45I1SG's variable-precision DSP blocks with hard IEEE 754 single-precision floating point accelerate pulse-Doppler, MTI, and digital-beamforming kernels at sample rates up to the transceiver ceiling. The I1 industrial temperature grade (-40C to +100C) satisfies most ground-vehicle and shipboard deployments, with optional E1 for harsher environments. The 900K logic elements hold multi-mode waveforms in a single device, reducing SWaP-C versus multi-FPGA legacy solutions.
Recommended
Broadcast Video Processing / Studio Infrastructure
The 10AX090S1F45I1SG supports uncompressed 4K/UHD video workflows through its multi-rate transceivers (SDI rates up to 12 Gbps via 4xSDI-3G aggregation on GX channels) and its generous embedded memory for line/frame buffers. Its hard PCIe Gen3 endpoint supports a direct host-attached capture/playback path at >7 GB/s, while the 624 user I/Os feed multiple HDMI/SDI bridges. Designers choose Arria 10 GX specifically because it integrates the SDI gearbox and color-space converter logic in fabric without forcing a separate ASSP.
Recommended
High-Performance Computing / Hardware Accelerator
The 10AX090S1F45I1SG's 900K logic elements and hard floating-point DSP blocks make it attractive as a co-processor/accelerator in HPC chassis where PCIe Gen3 x8 host connectivity delivers ~7.88 GB/s to host CPU memory. The DDR4 hard memory controller attaches to high-density DIMMs or HMC, while the 12.5 Gbps transceivers carry inter-FPDA links or 10/40G NIC fan-out. Compared with GPUs, FPGAs deliver deterministic latency and superior bit-level DSP efficiency for genomic, financial Monte-Carlo, and signal-processing kernels.
Recommended
Medical Imaging and Diagnostic Equipment
Ultrasound, CT, and MRI systems rely on beamformers, FFT/iFFT engines, and parallel sample pipelines that map directly onto the 10AX090S1F45I1SG's variable-precision DSP fabric. The hard floating-point blocks accelerate RF demodulation and image reconstruction, while the 624 I/Os interface to analog front-ends and the display subsystem. The I1 industrial temperature grade satisfies clinical and mobile-cart deployments, and the F45 1932-ball FCBGA provides the fine-pitch BGA needed for compact daughter cards inside imaging carts. Designers choose Arria 10 GX over mid-range FPGAs because the floating-point DSP is hard-IP, reducing logic and easing IEC 60601-1 EMC compliance.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090S1F45I1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090S1F45E1SG | 10AX090N3F45E2LG | 10AX090N4F45I3LG | 10AX090N2F45I1SG | 10AX090N2F45I2LG | 10AX090N2F45E2SG | 10AX090N2F45E1SG |
|---|---|---|---|---|---|---|---|---|
| Package | 1932-ball FCBGA (F45, 45mm) | 1932-ball FCBGA (F45, 45mm) - same | 1932-ball FCBGA (F45, 45mm) - same | 1932-ball FCBGA (F45, 45mm) - same | 1932-ball FCBGA (F45, 45mm) - same | 1932-ball FCBGA (F45, 45mm) - same | 1932-ball FCBGA (F45, 45mm) - same | 1932-ball FCBGA (F45, 45mm) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Embedded Memory | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits |
| Maximum User I/Os | 624 | 624 | 624 | 624 | 624 | 624 | 624 | 624 |
| Transceiver Speed Grade | S1 (12.5 Gbps) | S1 (12.5 Gbps) - same | N3 (10.3125 Gbps) - slower | N4 (10.3125 Gbps) - slower | N2 (6.144 Gbps) - slower | N2 (6.144 Gbps) - slower | N2 (6.144 Gbps) - slower | N2 (6.144 Gbps) - slower |
| Temperature Grade | Industrial I1 (-40C to +100C) | Extended E1 - wider | Extended E2 - wider | Industrial I3 - narrower | Industrial I1 - same | Industrial I2 - narrower | Extended E2 - wider | Extended E1 - wider |
| Hard PCIe Gen3 IP | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Process Node | 20nm | 20nm | 20nm | 20nm | 20nm | 20nm | 20nm | 20nm |
| Family | Arria 10 GX | Arria 10 GX | Arria 10 GX | Arria 10 GX | Arria 10 GX | Arria 10 GX | Arria 10 GX | Arria 10 GX |
Key Differentiators
- Highest transceiver rate (12.5 Gbps) in the Arria 10 GX F45-footprint family (vs 10AX090N2F45I1SG (N2 bin))
- Industrial temperature grade matches typical end-product operating envelope (vs 10AX090S1F45E1SG (E1 extended grade))
- Lower-cost alternative vs Stratix 10 while retaining hard floating-point DSP (vs 10AX115 Stratix 10 family parts)
Design Notes
The 1932-ball FCBGA F45 package requires a high-density PCB stack-up with controlled-impedance routing for the 12.5 Gbps transceiver channels. Per the Arria 10 GX board design guidelines, use a stack-up with at least 8 layers, microvia or stacked-via escape from the 0.8mm BGA pitch, and a continuous reference plane under the transceiver ball array. Estimated: total BGA fan-out may require at least 2 inner high-speed layers for the transceiver channels plus 2 more for DDR4 byte-group routing. Skipping the high-speed reference plane returns will degrade eye-diagram margin.
The 1932-ball FCBGA package relies primarily on the package top spreader and PCB copper thermal vias for heat removal. Estimated: with a typical 900K-LE Arria 10 design at 0.9V core, the device can dissipate 15-30W under load; size the heatsink per the Quartus Prime PowerPlay Early Power Estimator output. Ensure 25C or better thermal rise at the spreader by providing 4+ thermal vias per BGA thermal pad and a top-side heatsink with thermal interface material.
Common pitfalls when designing with the 10AX090S1F45I1SG include: (1) substituting an S1 speed bin with an N2/N3 bin without verifying the design does not rely on the 12.5 Gbps transceiver rate; (2) omitting the 100 MHz reference clock jitter cleaner (e.g., Si5341) on the REFCLK pin - the 12.5 Gbps link will fail eye-mask compliance; (3) using a generic non-validated JTAG programmer - use only Intel FPGA Download Cable II for production programming; (4) failing to instantiate the SmartVID controller - omitting it leaves the core voltage at the default, which is suboptimal for low-activity regions.
The transceiver channels require matched-length (within 0.127mm/5mil) routing with controlled 90-ohm differential impedance for the high-speed serial lanes. Use the Intel-provided Arria 10 GX transceiver channel planner to derive per-channel pre-emphasis and equalization taps; the IBIS-AMI models are required for system-level channel simulation. Estimated: total transceiver channel insertion loss must remain below the limit specified in the Arria 10 GX device datasheet (typically <10dB at 6.25 GHz for the S1 speed grade).
Compliance Information
RoHS compliance per Intel/Altera Arria 10 product family declaration. Halogen-free status not explicitly stated in verified data and marked unknown. AEC-Q100 not applicable - this is an FPGA, not an automotive-qualified IC.
