10AX090N4F45I3LG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Altera
MPN: 10AX090N4F45I3LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6503.71 | $6,503.71 |
| 10 | $6178.52 | $61,785.20 |
| 25 | $5853.34 | $146,333.50 |
| 50 | $5528.15 | $276,407.50 |
| 100 | $5202.97 | $520,297.00 |
Drop-in alternatives for 10AX090N4F45I3LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX090N3F45I3LG
✅ Drop-In📋 Reference alternative (not in catalog)
10AX090N3F45I2LG
✅ Drop-In✓ In Stock
$2995 / Unit
View Datasheet →10AX090N2F45I2LG
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →10AX090N2F45I1SG
✅ Drop-In✓ In Stock
$6450 / Unit
View Datasheet →10AX090N4F40I3LG
✅ Drop-In✓ In Stock
$3290 / Unit
View Datasheet →10AX066N2F40E1SG
✅ Drop-In✓ In Stock
$3350 / Unit
View Datasheet →10AX090N4F45I3LG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Family | 10AX090 |
| Logic Elements | 900,000 |
| Embedded Memory Bits | 59,234,304 |
| User I/Os | 768 |
| Package | 1932-BBGA, FCBGA |
| Package Code | F45 |
| Ball Count | 1932 |
| Process Technology | 14 nm Tri-Gate |
| Logic Structure | N4 |
| Speed Grade | -3 |
| Operating Temperature | -40C to +100C (Industrial) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AX090N4F45I3LG Pin Configuration
| Pin 1 | VCC — Core supply (0.85 V typical) - position approximate; see device datasheet pin tables for exact ball map |
| Pin 2 | GND — Ground reference |
| Pin 3 | IO_BANK_1A — User I/O in bank 1A |
| Pin 4 | IO_BANK_1B — User I/O in bank 1B |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090N4F45I3LG is suitable for 6 applications: 100G Optical Transport Platform, Wireless Baseband Processing, Radar and Electronic Warfare Beamforming, Broadcast Video Infrastructure, ASIC Prototyping and Emulation, Medical Imaging (CT/MRI Reconstruction).
100G Optical Transport Platform
The 10AX090N4F45I3LG drives 100G OTU4 optical transport cards where its 900K logic elements implement the MAC, PCS, and forward-error-correction (FEC) blocks, while the Arria 10 GX transceivers deliver up to 28.05 Gbps per lane for 4x25G or 4x28G optical interfaces. The 768 user I/Os comfortably fan out to multiple SFP+/QSFP cages plus a backplane. Placed as the line-card processor, it eliminates the need for an external FEC ASSP. Compared with smaller Arria 10 variants, the 900K LE density removes multi-FPGA partitioning at 100G line rate.
Recommended
Wireless Baseband Processing
In 4G/5G baseband units, the 10AX090N4F45I3LG's variable-precision DSP blocks execute single-precision floating-point operations required for channel estimation, MIMO detection, and FFT/iFFT pipelines. The 14 nm Tri-Gate process delivers the performance-per-watt needed for outdoor radio units. With 900K logic elements, a single device can host multiple LTE carriers or one 5G NR carrier. Compared with DSP-only ASSPs, the FPGA's reconfigurability supports multi-standard base stations across LTE, 5G NR, and proprietary waveforms.
Recommended
Radar and Electronic Warfare Beamforming
Phased-array radar and electronic-warfare systems use the 10AX090N4F45I3LG to perform digital beamforming across thousands of antenna elements. The Arria 10 GX transceivers handle the ADC/DAC JESD204B/C links, while the 900K logic elements implement beam-steering weights, calibration, and pulse compression. The industrial temperature range (-40C to +100C) suits outdoor radar installations. Compared with ASIC-based alternatives, the FPGA enables rapid waveform updates without re-spinning silicon.
Recommended
Broadcast Video Infrastructure
In 4K/8K broadcast studios and contribution encoders, the 10AX090N4F45I3LG handles multi-stream HEVC/H.264 encoding, deinterlacing, color-space conversion, and SDI/HDMI aggregation. The 768 user I/Os support multiple 12G-SDI links (4x for 8K), and the embedded memory (59 Mbits) buffers multi-frame look-ahead for encoder pipeline latency hiding. Industrial temperature grade suits outdoor broadcast vans. Compared with ASIC encoders, the FPGA enables codec parameter tuning per broadcaster.
Recommended
ASIC Prototyping and Emulation
The 10AX090N4F45I3LG is a workhorse in ASIC prototyping farms where multiple FPGAs partition a large ASIC RTL design. The 900K logic elements map approximately 18-22 million ASIC gates (with 4-5x logic over-subscription), and the 28 Gbps transceivers connect to high-speed protocol bridges. Compared with dedicated emulation systems, Arria 10 GX delivers 4-8x faster bring-up at lower cost per gate. The industrial temperature range supports bring-up labs without special cooling.
Recommended
Medical Imaging (CT/MRI Reconstruction)
In CT and MRI scanners, the 10AX090N4F45I3LG accelerates image reconstruction algorithms (filtered back-projection, iterative reconstruction) using its variable-precision DSP blocks. The high logic count and memory bandwidth enable real-time reconstruction at full scanner data rates. The 14 nm process keeps power dissipation manageable in the scanner-room thermal envelope. Compared with GPU-based reconstruction, FPGA implementations offer deterministic latency critical for synchronized scan acquisition.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090N4F45I3LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090N3F45I3LG | 10AX090N3F45I2LG | 10AX090N2F45I2LG | 10AX090N4F40I3LG |
|---|---|---|---|---|---|
| Package | 1932-BBGA, FCBGA (F45, 45 mm) | 1932-BBGA, FCBGA (F45) | 1932-BBGA, FCBGA (F45) | 1932-BBGA, FCBGA (F45) | 1517-BBGA, FCBGA (F40) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 900,000 | 900,000 | 900,000 | 660,000 | 900,000 |
| Embedded Memory (bits) | 59,234,304 | 59,234,304 | 59,234,304 | [DATA_NEEDED] | 59,234,304 |
| User I/Os | 768 | 768 | 768 | [DATA_NEEDED] | 688 |
| Speed Grade | -3 | -3 | -2 | -2 | -3 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Industrial | Industrial | Industrial |
| Approx. Unit Price (qty 1) | $6,503.71 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- N4 silicon revision vs earlier N3 revision (vs 10AX090N3F45I3LG)
- -3 speed grade offers highest Fmax in the Arria 10 family (vs 10AX090N3F45I2LG)
- 1932-ball F45 package vs 1517-ball F40 package for routing headroom (vs 10AX090N4F40I3LG)
Design Notes
The 1932-ball FCBGA package requires 12+ layer PCB stackup with 1.0 mm ball pitch escape routing. Use HDI micro-via (laser-drilled, 0.1 mm pad) fan-out from the BGA to inner signal layers; avoid through-hole vias in the inner 3x3 ball grid to preserve routability. Maintain a continuous GND reference plane beneath the device for return-path integrity and thermal spreading. Reference the Altera Arria 10 GX PCB Design Guidelines for stackup recommendations.
At -3 speed grade the 10AX090N4F45I3LG can dissipate 25-40 W depending on toggle rate and transceiver utilization. Use a heat sink with thermal interface material (TIM), and provide at least 400 LFM airflow for industrial-temperature operation. The package top is the primary thermal path; exposed-die variant requires a heat sink with 4 N downward force. Estimate: junction-to-ambient theta_JA ~ 4-6 C/W with heat sink at 400 LFM.
Multi-rail power delivery is required: 0.85 V core (20-30 A load), 1.2 V/1.8 V/2.5 V/3.3 V auxiliary I/O rails (3-5 A each), and a dedicated transceiver PLL supply (1.0 V filtered). Use a Powertrain or equivalent sequencer for controlled power-up/down, and place decoupling within 100 mil of each supply ball. Reference the Altera Arria 10 GX Power Distribution Network design guide for decoupling density.
Do not mix the N3 and N4 logic revision codes without verifying against the latest Intel PCN database - some early N4 silicon has documented errata fixed in later N3 revisions. Do not assume 10AX090 (F45) is pin-compatible with 10AX066 (F40) - different ball counts (1932 vs 1517) require different PCB footprints. Always lock the device pin-out using Quartus Prime Pin Planner before PCB fab.
Compliance Information
RoHS compliant per Altera/Intel product page. The 'LG' suffix in the part number indicates lead-free finish (matte-tin). Not AEC-Q100 qualified - Arria 10 GX is not marketed for automotive safety-critical applications.
