10AX115N3F45E2LG - Arria 10 GX 1.15M LE FPGA | Intel | 1932-FCBGA
MPN: 10AX115N3F45E2LG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5800 | $5,800.00 |
| 10 | $5450 | $54,500.00 |
| 100 | $4980 | $498,000.00 |
| 500 | $4620 | $2,310,000.00 |
| 1,000 | $4325 | $4,325,000.00 |
Drop-in alternatives for 10AX115N3F45E2LG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AX115N3F45E2SG
β Drop-Inβ In Stock
$3100 / Unit
View Datasheet β10AX115N3F45E1SG
β Drop-Inπ Reference alternative (not in catalog)
10AX115N3F45I2SG
β Drop-Inβ In Stock
$5200 / Unit
View Datasheet β10AX115N2F45E2LG
β Drop-Inβ In Stock
$7580.55 / Unit
View Datasheet β10AX090N3F45E2LG
β Drop-Inβ In Stock
$2285 / Unit
View Datasheet β10AX115N3F45E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 1,150,000 |
| Embedded Memory | 68,857,856 bits |
| User I/O Count | 768 |
| Transceiver Data Rate (max) | 28.05 Gbps |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Operating Temperature Grade | Extended (E2) |
| Package | 1932-ball FCBGA (F45) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AX115N3F45E2LG Pin Configuration
| Pin A1 | I/O β General-purpose user I/O; refer to pinout file for assigned bank |
| Pin A2 | I/O β General-purpose user I/O; refer to pinout file for assigned bank |
| Pin B1 | I/O β General-purpose user I/O; refer to pinout file for assigned bank |
| Pin B2 | GND β Ground reference |
| Pin C1 | VCC β Core supply (0.9 V) |
| Pin C2 | VCCAUX β Auxiliary supply (typically 1.8 V or 2.5 V) |
| Pin D1 | I/O β High-speed user I/O or clock input; refer to pinout file |
| Pin D2 | I/O β High-speed user I/O or clock input; refer to pinout file |
| Pin E1 | GXB_TX β Transceiver transmit differential pair |
| Pin E2 | GXB_RX β Transceiver receive differential pair |
| Pin F1 | I/O β User I/O |
| Pin F2 | I/O β User I/O |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX115N3F45E2LG is suitable for 6 applications: 4K/UHD Video Broadcast Encoding and Decoding, 5G Wireless Baseband and Remote Radio Units, Military Radar and Electronic Warfare, Medical Imaging Acceleration, ASIC Prototyping and Emulation, Test and Measurement Instrumentation.
4K/UHD Video Broadcast Encoding and Decoding
The 10AX115N3F45E2LG is well suited to 4K/UHD video broadcast encoding and decoding because its 1,150,000 logic elements and hardened floating-point DSP blocks can sustain multiple HEVC/H.264 streams at 60 fps without external co-processors. The 768 user I/O enable direct attachment of multiple SDI/HDMI interfaces and frame buffers, while the 28.05 Gbps transceivers handle SMPTE ST 2022/2110 uncompressed video over 25G Ethernet. Compared to a generic FPGA, the Arria 10 GX family offers an integrated video IP suite in Quartus Prime that reduces time-to-market for broadcast equipment designers.
Recommended
5G Wireless Baseband and Remote Radio Units
In 5G wireless baseband and remote radio head (RRH) designs, the 10AX115N3F45E2LG delivers the DSP throughput required for massive-MIMO beamforming and CPRI/eCPRI fronthaul. The 28.05 Gbps transceivers and 768 user I/O allow direct interface to multiple AD9361-class transceivers and high-speed data converters, while the 68 Mbit of embedded memory provides the buffers required for sub-millisecond latency. Its 20 nm process and SmartVID reduce power dissipation compared to prior 28 nm generations, critical for outdoor radio units with thermal constraints.
Recommended
Military Radar and Electronic Warfare
The 10AX115N3F45E2LG fits military radar and electronic warfare (EW) systems where its high logic density enables real-time pulse compression, beamforming, and adaptive signal processing. The 28.05 Gbps transceivers support direct connection to high-speed ADCs/DACs in radar front-ends, while the hardened DSP blocks accelerate FFT and matrix operations central to digital beamforming. The F45 1932-ball FCBGA package provides the thermal performance and signal integrity required for ruggedized environments, and the Arria 10's 20 nm process node offers a balance of radiation tolerance considerations and power efficiency.
Recommended
Medical Imaging Acceleration
In medical imaging applications such as CT, MRI, and ultrasound, the 10AX115N3F45E2LG enables real-time image reconstruction by offloading computationally intensive back-projection and FFT operations from the host processor. The hardened floating-point DSP blocks provide IEEE 754 single-precision throughput in excess of 1 TFLOP, while the 768 I/O pins allow direct connection to high-speed data converters and image sensors. The 0.9 V core voltage and 20 nm process reduce power dissipation, important for cart-mounted imaging systems.
Recommended
ASIC Prototyping and Emulation
The 10AX115N3F45E2LG is widely used as an ASIC prototyping and emulation platform because its 1.15 M logic elements can map large RTL designs with high visibility and debug capability. The 768 user I/O provide extensive pin multiplexing for partitioning large ASIC designs across multiple FPGAs, while the 28.05 Gbps transceivers enable high-speed chip-to-chip links between FPGAs in a multi-board emulation chassis. Designers use the Quartus Prime Pro Edition's TimeQuest timing analyzer and SignalTap logic analyzer for thorough verification before ASIC tape-out.
Recommended
Test and Measurement Instrumentation
In test and measurement instrumentation such as high-speed oscilloscopes, arbitrary waveform generators, and protocol analyzers, the 10AX115N3F45E2LG provides parallel DSP throughput for real-time signal processing. The 28.05 Gbps transceivers allow direct acquisition of multi-GHz serial data streams (PCIe Gen3, USB 3.1, SATA) for protocol analysis, while the 768 user I/O support multiple display, trigger, and front-panel interfaces. The deterministic latency and large embedded memory help designers achieve sub-microsecond trigger-to-acquisition timing accuracy.
Recommended
Recommended Products Summary
Engineering reference data for 10AX115N3F45E2LG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX115N3F45E2SG | 10AX115N3F45E1SG | 10AX115N3F45I2SG | 10AX115N2F45E2LG | 10AX090N3F45E2LG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1932-ball FCBGA (F45) | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same | 1932-ball FCBGA (F45) - same |
| Logic Elements | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 1,150,000 | 900,000 |
| User I/O Count | 768 | 768 | 768 | 768 | 768 | 768 |
| Speed Grade | -2 (E2) | -2 (E2) | -1 (slower) | -2 (I2) | -2 (N2) | -2 (E2) |
| Temperature Grade | Extended commercial (E2) | Extended commercial (E2) | Extended commercial (E1) | Industrial (I2) | Extended commercial (E2) | Extended commercial (E2) |
| Embedded Memory (Mbits) | 68.86 | 68.86 | 68.86 | 68.86 | 68.86 | 53.5 |
| Max Transceiver Rate | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 17.4 Gbps (N2) | 28.05 Gbps |
Key Differentiators
- Highest-density Arria 10 GX with 1.15M logic elements (vs 10AX090N3F45E2LG)
- Highest transceiver speed grade in the family (N3) (vs 10AX115N2F45E2LG)
- Extended commercial temperature grade with industrial migrability (vs 10AX115N3F45I2SG)
Design Notes
The Arria 10 GX requires a multi-rail power distribution network: 0.9 V core, 1.8 V or 2.5 V VCCAUX, dedicated transceiver rails (VCCPT, VCCR_GXB, VCCT_GXB), and I/O bank voltages. Use SmartVID with a dedicated PMBus controller (such as the LTM4677 or EM21xx) to optimize core voltage based on the device's speed bin and process corner. Decoupling requires a mix of bulk, mid-frequency, and high-frequency capacitors within 100 mils of the balls; follow Intel's PDN design guidelines for the 20 nm node.
In the 1932-ball FCBGA F45 package, thermal dissipation depends heavily on the PCB stack-up and airflow. At full transceiver utilization (all lanes at 28.05 Gbps) and high DSP utilization, the device can dissipate 20-30 W. Use a minimum 12-layer PCB with thermal vias under the exposed die pad, and consider attaching a heatsink for closed enclosures. Intel's Quartus Prime PowerPlay estimator is required for an accurate power budget before PCB layout.
The F45 1932-ball FCBGA requires a 1.0 mm ball pitch and a high-density interconnect PCB with microvias (stacked or staggered). High-speed transceiver channels demand matched 85-ohm or 100-ohm differential impedance with length-matching to within 5 mils across P and N, and skew control across lanes within 150 ps. Reference Intel's Arria 10 board design guidelines for the exact via pattern, escape routing, and stack-up recommendations.
Common pitfalls include: (1) using the wrong Quartus Prime device pinout file for the specific MPN; (2) failing to enable the SmartVID interface - the device will not configure if the controller is absent; (3) forgetting MSL handling for the FCBGA package - the device is moisture-sensitive and requires baking per JEDEC J-STD-033 before reflow; (4) under-provisioning the configuration flash (EPCQ-L) bitstream storage.
Compliance Information
RoHS compliance and lead-free status per Altera/Intel product page ordering code suffix 'LG' (lead-free). AEC-Q100 not applicable - this is a commercial/industrial-grade FPGA. Halogen-free status not explicitly listed in the verified data.
