5M160ZE64I5 - MAX V CPLD, 160 LE, 54 I/O, EQFP-64 | Intel
MPN: 5M160ZE64I5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.36 | $6.36 |
| 10 | $5.72 | $57.20 |
| 100 | $5.1 | $510.00 |
| 500 | $4.59 | $2,295.00 |
| 1,000 | $4.1 | $4,100.00 |
Drop-in alternatives for 5M160ZE64I5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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5M160ZE64I5N
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$4.13 / Unit
View Datasheet →5M160ZE64I4N
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Contact for price
View Datasheet →5M160ZE64C5N
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$4.95 / Unit
View Datasheet →5M160ZE64C5
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$4.85 / Unit
View Datasheet →5M160ZE64C4N
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$4.3 / Unit
View Datasheet →5M160ZE64A5N
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$6.2 / Unit
View Datasheet →5M160ZE64I5 Maximum Ratings & Electrical Characteristics
| Device Family | MAX V |
| Device Type | SPLD / CPLD |
| Logic Elements | 160 |
| User I/Os | 54 |
| Total Pins | 64 |
| Package | EQFP-64 (Plastic, 9 x 9 mm, 0.40 mm pitch) |
| Mounting Type | Surface Mount (Gull Wing) |
| Configuration Memory | Flash, non-volatile |
| Internal User Flash (UFM) | 8 Kbits |
| Internal Frequency (max) | 118.3 MHz |
| Propagation Delay (tPD, max) | 7.9 ns |
| Internal Frequency (typical) | 184 MHz |
| Supply Voltage VCCINT | 1.8 V (typ) |
| I/O Supply Voltage VCCIO | 1.2 V to 3.3 V (MultiVolt) |
| Operating Temperature | -40C to +100C (industrial, I-grade) |
| Programming Interface | JTAG (IEEE 1149.1) + ISP |
| RoHS Status | Compliant |
5M160ZE64I5 Pin Configuration
| Pin 1 | I/O — User I/O bank 1 |
| Pin 2 | I/O — User I/O bank 1 |
| Pin 3 | I/O — User I/O bank 1 |
| Pin 4 | GND — Ground |
| Pin 5 | I/O — User I/O bank 1 |
| Pin 6 | I/O — User I/O bank 1 |
| Pin 7 | I/O — User I/O bank 1 |
| Pin 8 | I/O — User I/O bank 1 |
| Pin 9 | I/O — User I/O bank 2 |
| Pin 10 | I/O — User I/O bank 2 |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O bank 2 |
| Pin 13 | I/O — User I/O bank 2 |
| Pin 14 | I/O — User I/O bank 2 |
| Pin 15 | I/O — User I/O bank 2 |
| Pin 16 | I/O — User I/O bank 2 |
| Pin 17 | I/O — User I/O bank 3 |
| Pin 18 | I/O — User I/O bank 3 |
| Pin 19 | I/O — User I/O bank 3 |
| Pin 20 | I/O — User I/O bank 3 |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O bank 3 |
| Pin 23 | I/O — User I/O bank 3 |
| Pin 24 | I/O — User I/O bank 3 |
| Pin 25 | I/O — User I/O bank 3 |
| Pin 26 | I/O — User I/O bank 4 |
| Pin 27 | I/O — User I/O bank 4 |
| Pin 28 | I/O — User I/O bank 4 |
| Pin 29 | I/O — User I/O bank 4 |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — User I/O bank 4 |
| Pin 32 | I/O — User I/O bank 4 |
| Pin 33 | I/O — User I/O bank 4 |
| Pin 34 | I/O — User I/O bank 4 |
| Pin 35 | I/O — User I/O bank 1 |
| Pin 36 | I/O — User I/O bank 1 |
| Pin 37 | I/O — User I/O bank 1 |
| Pin 38 | I/O — User I/O bank 1 |
| Pin 39 | GND — Ground |
| Pin 40 | I/O — User I/O bank 1 |
| Pin 41 | I/O — User I/O bank 1 |
| Pin 42 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 43 | TMS — JTAG Test Mode Select |
| Pin 44 | TCK — JTAG Test Clock |
| Pin 45 | TDO — JTAG Test Data Out |
| Pin 46 | GND — Ground |
| Pin 47 | VCCIO — I/O supply voltage (1.2 V - 3.3 V) |
| Pin 48 | VCCIO — I/O supply voltage (1.2 V - 3.3 V) |
| Pin 49 | I/O — User I/O bank 2 |
| Pin 50 | I/O — User I/O bank 2 |
| Pin 51 | I/O — User I/O bank 2 |
| Pin 52 | I/O — User I/O bank 2 |
| Pin 53 | GND — Ground |
| Pin 54 | I/O — User I/O bank 3 |
| Pin 55 | I/O — User I/O bank 3 |
| Pin 56 | I/O — User I/O bank 3 |
| Pin 57 | I/O — User I/O bank 3 |
| Pin 58 | VCCIO — I/O supply voltage (1.2 V - 3.3 V) |
| Pin 59 | VCCIO — I/O supply voltage (1.2 V - 3.3 V) |
| Pin 60 | GND — Ground |
| Pin 61 | VCCINT — Core supply voltage (1.8 V) |
| Pin 62 | VCCINT — Core supply voltage (1.8 V) |
| Pin 63 | I/O — User I/O bank 4 |
| Pin 64 | I/O — User I/O bank 4 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZE64I5 is suitable for 6 applications: Bus-Bridging and Glue Logic, I/O Expansion and Level Translation, Power Sequencing and Reset Distribution, LED Display Driving and Scan Control, Industrial Control State Machines, Replacing Discrete 74-Series Logic.
Bus-Bridging and Glue Logic
The 5M160ZE64I5 is well suited to bridge legacy parallel buses (e.g., 8/16-bit 5V-tolerant interfaces) to modern 1.8 V or 3.3 V MCUs thanks to its 54 MultiVolt I/O pins that support 1.2 V to 3.3 V levels in independently configurable banks. The 7.9 ns tPD lets it register and re-time signals within a single bus cycle, while 160 Logic Elements are enough to implement several bus-state machines concurrently. Instant-on flash configuration means the bridge is active within microseconds of power-up, eliminating the boot-delay seen with SRAM-based FPGAs. Engineers typically use the Quartus Prime II toolchain to compile the bridge Verilog and program via JTAG.
Recommended
I/O Expansion and Level Translation
With 54 user I/Os and MultiVolt I/O banks, the 5M160ZE64I5 acts as a flexible I/O expander that can simultaneously drive 1.8 V, 2.5 V, and 3.3 V peripherals from a single 1.8 V core supply. The flash-based non-volatile configuration lets it hold its expansion personality across power cycles without an external PROM. Designers use the device to fan-out GPIOs from a pin-limited MCU, translate between SD card and SoC voltage rails, or build hot-swap controllers. Compared to discrete level shifters the CPLD approach reduces BOM count and offers software-reconfigurable pin direction and pull-ups.
Recommended
Power Sequencing and Reset Distribution
The 5M160ZE64I5 is commonly used as a programmable power-sequencer and reset-distributor in industrial and telecom boards. Its 160 Logic Elements and 54 I/Os are sufficient to monitor up to a dozen power-good lines, generate sequenced enable signals with millisecond delays, and drive multiple reset outputs with defined pulse widths. The 1.8 V core operates directly from an intermediate system rail, and the I/O banks can handshake with 3.3 V supervisors without external glue. Predictable 7.9 ns tPD helps the sequencer react quickly to fault conditions, and the JTAG interface lets firmware updates of the sequence be pushed in-system.
Recommended
LED Display Driving and Scan Control
Industrial and signage LED displays rely on fast row-scan multiplexing that benefits from the deterministic timing of a CPLD like the 5M160ZE64I5. With 54 I/Os it can directly drive multiplexed 7-segment or dot-matrix panels up to 16 rows without an external driver, and its 118.3 MHz fMAX keeps refresh rates well above the flicker threshold. The built-in 8 Kbit user flash memory (UFM) can store brightness tables and animation patterns in non-volatile storage, accessed via JTAG or a simple SPI interface. The industrial -40C to +100C range matches outdoor and factory-floor thermal requirements without derating.
Recommended
Industrial Control State Machines
PLC-style controllers and motor-drive signal-conditioning boards often need deterministic state machines that the 5M160ZE64I5 implements in 160 Logic Elements with predictable, single-clock-cycle latency. The 1.8 V core plus MultiVolt I/O lets the CPLD sit directly on a 24 V industrial bus after isolation, communicating with 3.3 V sensors and 5 V actuators from the same die. The non-volatile flash configuration boots into a known-good state on every power cycle, a critical feature for safety-rated machinery. Combined with the JTAG interface, field upgrades of the state machine are possible without removing the part from the panel.
Recommended
Replacing Discrete 74-Series Logic
Designers often replace dozens of 74HC/74AHC/74LVT glue-logic gates with a single 5M160ZE64I5 to save PCB area, reduce BOM, and gain reconfigurability. A 64-pin EQFP part replaces tens of SOT-23 and SOIC gates while exposing the logic as Quartus Verilog rather than hard-wired traces. The instant-on flash configuration means no boot delay, and JTAG programming lets the logic be updated at the factory or in the field. Power consumption is comparable to a handful of CMOS gates at the -40C to +100C industrial temperature grade.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZE64I5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZE64I5N | 5M160ZE64I4N | 5M160ZE64C5N | 5M160ZE64C5 | 5M160ZE64C4N | 5M160ZE64A5N |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | EQFP-64 (9x9 mm, 0.40 mm pitch) | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same | EQFP-64 - same |
| Logic Elements | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| User I/Os | 54 | 54 | 54 | 54 | 54 | 54 | 54 |
| Speed Grade | -5 (fastest) | -5 | -4 (slower) | -5 | -5 | -4 (slower) | -5 |
| Temperature Grade | Industrial -40C to +100C | Industrial | Industrial | Commercial 0C to +85C | Commercial 0C to +85C | Commercial 0C to +85C | Extended (A-grade) |
| Propagation Delay tPD (max) | 7.9 ns | 7.9 ns | Slower (grade -4) | 7.9 ns | 7.9 ns | Slower (grade -4) | 7.9 ns |
| Max Internal Frequency | 118.3 MHz | 118.3 MHz | Lower (grade -4) | 118.3 MHz | 118.3 MHz | Lower (grade -4) | 118.3 MHz |
| VCCINT | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Configuration Memory | Flash (non-volatile) | Flash | Flash | Flash | Flash | Flash | Flash |
Key Differentiators
- Smallest MAX V CPLD with full industrial temp grade (vs 5M1270ZT144I5)
- Same-package pin-compatible across all temperature and speed grades (vs 5M160ZE64C5)
- MultiVolt I/O supports mixed-voltage interfaces on one die (vs Discrete 74-series level shifters)
Design Notes
Estimated: with VCCINT = 1.8 V at ~25 mA typical core current and VCCIO = 3.3 V at ~10 mA for 54 active I/Os, total steady-state power is approximately 0.08 W. Provide at least one 0.1 uF X7R ceramic decoupling capacitor at each VCCINT pin and one at each VCCIO pin, placed within 3 mm of the package pad. Add a 4.7 uF bulk tantalum or ceramic cap at the supply entry to the CPLD region. Failure to decouple properly can show up as JTAG programming errors and intermittent I/O glitches.
The 64-pin EQFP package is 9 x 9 mm with 0.40 mm pin pitch and gull-wing leads. Use a 4-layer PCB with a continuous ground plane beneath the device to keep the JTAG signals clean and to provide a thermal sink for the low-power die. Keep TCK away from fast-switching I/O traces; if routing density forces proximity, add a ground guard trace between TCK and adjacent signals. Pull TMS and TDI up to VCCIO through 10 kohm resistors if the JTAG chain is unused, to keep the TAP controller in a benign state.
Do not drive the JTAG TCK pin with a faster signal than the device's ISP limit, or programming will fail intermittently. Do not leave unused I/O pins floating - configure them as outputs driving low in the Quartus pin-assignment file to minimise leakage and EMI. Mixing VCCIO banks above 3.3 V is not supported; design all bank voltages within the 1.2 V to 3.3 V MultiVolt range stated in the MAX V Device Handbook. Finally, verify the device's industrial -40C to +100C range meets your enclosure's worst-case ambient, especially in unventilated outdoor cabinets.
Compliance Information
RoHS compliance per Intel/Altera MAX V product family documentation. Lead-free finish on the N-suffix variants; non-N variants should be qualified against your RoHS scope. AEC-Q100 not applicable - this is a commercial/industrial CPLD, not an automotive-qualified IC.
