5M80ZE64C5N - MAX V CPLD, 64 Macrocells, 118.3 MHz | Intel
MPN: 5M80ZE64C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.76 | $4.76 |
| 10 | $4.28 | $42.80 |
| 100 | $3.62 | $362.00 |
| 500 | $2.98 | $1,490.00 |
| 1,000 | $2.51 | $2,510.00 |
Drop-in alternatives for 5M80ZE64C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M80ZE64I5N
β Drop-Inβ In Stock
$4.1 / Unit
View Datasheet β5M80ZE64C4N
β Drop-Inβ In Stock
$2.1 / Unit
View Datasheet β5M160ZE64C5N
β Drop-Inβ In Stock
$4.95 / Unit
View Datasheet β5M160ZE64I5N
β Drop-Inβ In Stock
$4.13 / Unit
View Datasheet β5M240ZE64A5N
β Drop-Inπ Reference alternative (not in catalog)
5M80ZE64C5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device Logic Elements | 80 |
| Number of Macrocells | 64 |
| Maximum Internal Frequency | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns (commercial, per datasheet summary) |
| User I/Os | 54 |
| Core Voltage | 1.8 V |
| Programmable Configuration Memory | Flash (non-volatile) |
| Package | 64-pin EQFP (E64) with exposed pad |
| Mounting Type | Surface Mount |
| I/O Standards Supported | LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V |
| JTAG Support | IEEE 1149.1 compliant boundary-scan |
| Operating Temperature Range | 0C to +85C (commercial, C5N suffix) |
| RoHS Status | Compliant (per distributor listings) |
| Lead-Free | Yes (per distributor listings) |
5M80ZE64C5N Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (bank 1) |
| Pin 2 | I/O β General-purpose user I/O (bank 1) |
| Pin 3 | I/O β General-purpose user I/O (bank 1) |
| Pin 4 | I/O β General-purpose user I/O (bank 1) |
| Pin 5 | I/O β General-purpose user I/O (bank 1) |
| Pin 6 | I/O β General-purpose user I/O (bank 1) |
| Pin 7 | I/O β General-purpose user I/O (bank 1) |
| Pin 8 | I/O β General-purpose user I/O (bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β General-purpose user I/O (bank 2) |
| Pin 11 | I/O β General-purpose user I/O (bank 2) |
| Pin 12 | I/O β General-purpose user I/O (bank 2) |
| Pin 13 | I/O β General-purpose user I/O (bank 2) |
| Pin 14 | I/O β General-purpose user I/O (bank 2) |
| Pin 15 | I/O β General-purpose user I/O (bank 2) |
| Pin 16 | I/O β General-purpose user I/O (bank 2) |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β General-purpose user I/O (bank 2) |
| Pin 19 | I/O β General-purpose user I/O (bank 2) |
| Pin 20 | I/O β General-purpose user I/O (bank 2) |
| Pin 21 | I/O β General-purpose user I/O (bank 2) |
| Pin 22 | I/O β General-purpose user I/O (bank 2) |
| Pin 23 | I/O β General-purpose user I/O (bank 2) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β General-purpose user I/O (bank 2) |
| Pin 26 | I/O β General-purpose user I/O (bank 2) |
| Pin 27 | I/O β General-purpose user I/O (bank 2) |
| Pin 28 | I/O β General-purpose user I/O (bank 2) |
| Pin 29 | I/O β General-purpose user I/O (bank 2) |
| Pin 30 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 31 | I/O β General-purpose user I/O (bank 3) |
| Pin 32 | I/O β General-purpose user I/O (bank 3) |
| Pin 33 | I/O β General-purpose user I/O (bank 3) |
| Pin 34 | I/O β General-purpose user I/O (bank 3) |
| Pin 35 | I/O β General-purpose user I/O (bank 3) |
| Pin 36 | I/O β General-purpose user I/O (bank 3) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β General-purpose user I/O (bank 3) |
| Pin 39 | I/O β General-purpose user I/O (bank 3) |
| Pin 40 | I/O β General-purpose user I/O (bank 3) |
| Pin 41 | I/O β General-purpose user I/O (bank 3) |
| Pin 42 | I/O β General-purpose user I/O (bank 3) |
| Pin 43 | TDI β JTAG test data input |
| Pin 44 | TMS β JTAG test mode select |
| Pin 45 | TCK β JTAG test clock |
| Pin 46 | TDO β JTAG test data output |
| Pin 47 | I/O β General-purpose user I/O (bank 4) |
| Pin 48 | I/O β General-purpose user I/O (bank 4) |
| Pin 49 | I/O β General-purpose user I/O (bank 4) |
| Pin 50 | I/O β General-purpose user I/O (bank 4) |
| Pin 51 | I/O β General-purpose user I/O (bank 4) |
| Pin 52 | GND β Ground |
| Pin 53 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 54 | I/O β General-purpose user I/O (bank 4) |
| Pin 55 | I/O β General-purpose user I/O (bank 4) |
| Pin 56 | I/O β General-purpose user I/O (bank 4) |
| Pin 57 | I/O β General-purpose user I/O (bank 4) |
| Pin 58 | VCCINT β Internal core supply (1.8 V) |
| Pin 59 | I/O β General-purpose user I/O (bank 1) |
| Pin 60 | I/O β General-purpose user I/O (bank 1) |
| Pin 61 | I/O β General-purpose user I/O (bank 1) |
| Pin 62 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 63 | I/O β General-purpose user I/O (bank 1) |
| Pin 64 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZE64C5N is suitable for 6 applications: Industrial Glue Logic and I/O Expansion, Power-Up Sequencing in Multi-Rail Systems, Networking Line-Card Glue Logic, Consumer Electronics Interface Expansion, Automotive Body and Comfort Modules, Portable and Battery-Powered Devices.
Industrial Glue Logic and I/O Expansion
The 5M80ZE64C5N fits industrial glue logic roles because its 64 macrocells and 118.3 MHz internal frequency are well matched to bus-bridging, peripheral multiplexing, and signal-conditioning tasks that sit between a host microcontroller and external sensors or actuators. With 54 user I/Os in the 64-pin EQFP, the part can fan out a single MCU bus into multiple SPI/I2C/UART peripherals, offload custom timing logic from the MCU, and provide deterministic instant-on sequencing. The flash-based non-volatile configuration eliminates external boot storage, reducing BOM and board area in factory automation and process-control equipment.
Recommended
Power-Up Sequencing in Multi-Rail Systems
The 5M80ZE64C5N is a strong fit for power-up sequencing because its non-volatile flash configuration comes up in a defined state the instant VCC is stable - no FPGA configuration wait time. Engineers commonly program simple state machines in its 64 macrocells to assert enables to downstream LDOs, gate clocks, and release reset lines in the correct order. Its 1.8 V core and LVCMOS I/O support allow direct connection to typical 3.3 V power-good signals through level shifters, while 7.5 ns pin-to-pin delay keeps sequence timing well within sub-microsecond budgets.
Recommended
Networking Line-Card Glue Logic
In networking line cards, the 5M80ZE64C5N provides compact glue logic between PHYs, switch ASICs, and management controllers. Its 54 user I/Os handle MDIO/MDC bus steering, LED status driving, interrupt aggregation, and hardware revision strapping, while the 118.3 MHz internal frequency comfortably decodes GMII/RGMII-side timing helpers. The E64 EQFP footprint fits the tight pitch typical of line-card PCB assemblies, and the flash-based bitstream avoids the extra configuration memory that an FPGA of similar capability would require.
Recommended
Consumer Electronics Interface Expansion
The 5M80ZE64C5N is ideal for consumer electronics that need flexible I/O expansion without the cost or boot delay of an FPGA. Designs use its 64 macrocells to drive key-scan matrices, expand GPIO from an application processor, implement capacitive-touch sensing helpers, and provide LCD segment or LED matrix timing. The 1.8 V core and small E64 footprint simplify two-layer PCB layouts, while flash-based non-volatility means the device is fully functional the moment power is applied - critical for remote controls, appliances, and low-cost set-top boxes.
Recommended
Automotive Body and Comfort Modules
For automotive body and comfort modules - such as window controllers, mirror adjusters, and HVAC interfaces - the 5M80ZE64C5N delivers deterministic instant-on logic in a small EQFP package. Designers implement LIN/CAN bus helpers, debounce state machines, and PWM generation for motor drivers across its 54 user I/Os. For automotive-temperature applications that need the wider -40C to +125C range, designers use the 5M240ZE64A5N (automotive grade) in the same E64 footprint, simplifying migration paths while preserving PCB layout.
Recommended
Portable and Battery-Powered Devices
The 5M80ZE64C5N's low static power consumption and 1.8 V core make it a strong fit for portable, battery-powered products where every microwatt matters. Engineers use its 64 macrocells to implement low-duty-cycle control logic, sensor wake-up sequencers, and user-input pre-processing while the main MCU sleeps. The non-volatile flash means no configuration current is drawn at power-up, and the 64-pin EQFP package is small enough to fit handhelds, wearables, and wireless sensor nodes.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZE64C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M80ZE64I5N | 5M80ZE64C4N | 5M160ZE64C5N | 5M160ZE64I5N | 5M240ZE64A5N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 64-pin EQFP (E64) | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same |
| Macrocells | 64 | 64 (same die) | 64 (same die) | 160 (+150%) | 160 (+150%) | 240 (+275%) |
| Maximum Internal Frequency | 118.3 MHz | 118.3 MHz (same) | lower (C4 speed grade) | 118.3 MHz (same) | 118.3 MHz (same) | 118.3 MHz (same family) |
| Operating Temperature Range | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | automotive grade |
| User I/Os | 54 | 54 (same) | 54 (same) | 54 (same E64 pinout) | 54 (same) | 54 (same E64 pinout) |
| Core Voltage | 1.8 V | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) | 1.8 V (same family) |
| Configuration Memory | Flash (non-volatile) | Flash (same) | Flash (same) | Flash (same) | Flash (same) | Flash (same family) |
Key Differentiators
- Higher macro density than legacy MAX II in same E64 footprint (vs MAX II E64 family)
- Non-volatile flash configuration eliminates boot PROM (vs SRAM-based FPGAs in similar density)
- Industrial- and automotive-grade variants in same footprint (vs 5M80ZE64C5N commercial grade)
Design Notes
The 64-pin EQFP package includes an exposed thermal pad on the underside that, per the Intel MAX V Device Family Pin Connection Guidelines, must be soldered to the PCB ground plane. This pad is an electrical (not thermal) connection: it bonds the internal substrate ground to the board ground and is required for EMI and latch-up performance. Use at least six thermal vias in the pad to the ground plane, and ensure the ground pour is solid with no signal traces routed directly under the exposed pad to avoid stitching discontinuities.
Decouple the 5M80ZE64C5N with a 100 nF ceramic capacitor placed within 5 mm of each VCCINT and VCCIOx pin. Bulk-decouple each supply rail with a 10 uF tantalum or ceramic capacitor at the regulator output. The device supports separate VCCIOx bank voltages (typically 1.5/1.8/2.5/3.3 V), so per-bank bulk capacitors are recommended if multiple bank voltages are used. Sequence VCCINT before VCCIOx if the application is sensitive to I/O behavior at power-up.
Do not mix 1.5 V and 3.3 V signals on the same I/O bank without verifying the VCCIOx level - the I/O bank voltage sets the input threshold and output drive level for every pin in the bank. Mixing voltages across banks is fine, but mixing them within a bank will cause logic errors or device damage. When migrating designs between MAX V speed grades (C4, C5, I5), regenerate the bitstream in Quartus Prime rather than reusing a compiled file, because timing models differ between grades.
Compliance Information
RoHS compliance and lead-free status per DigiKey/Mouser distributor listings as of 2026-09-06. AEC-Q100 qualification not applicable to the C5N commercial grade; the 5M240ZE64A5N (auto grade variant) in the same family is AEC-Q100 qualified for automotive applications.
