5M80ZE64C4N - MAX V CPLD, 64 LE, 184MHz, 1.8V | Intel/Altera
MPN: 5M80ZE64C4N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.52 | $3.52 |
| 10 | $3.17 | $31.70 |
| 100 | $2.81 | $281.00 |
| 500 | $2.46 | $1,230.00 |
| 1,000 | $2.1 | $2,100.00 |
Drop-in alternatives for 5M80ZE64C4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
5M80ZE64C4/I5N
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet β5M80ZE64C4
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$4 / Unit
View Datasheet β5M80ZE64A5N
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$3.05 / Unit
View Datasheet β5M160ZE64C4N
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$4.3 / Unit
View Datasheet β5M160ZE64C5N
β Drop-Inβ In Stock
$4.95 / Unit
View Datasheet β5M40ZE64C4N
β Drop-Inβ In Stock
$1.7 / Unit
View Datasheet β5M80ZE64C4N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Device Logic Elements | 64 |
| Number of Macro Cells | 64 |
| Number of Logic Array Blocks (LABs) | 4 |
| Maximum User I/O Pins | 79 |
| Maximum Operating Frequency | 184.1 MHz |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Configuration Memory | Non-volatile flash, instant-on |
| Global Clocks | 2 |
| User Flash Memory | On-chip (8 Kbits) |
| Operating Temperature Grade | Commercial (0C to +85C) |
| Speed Grade | C4 |
| Package | 64-pin EQFP (E64) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (lead-free) |
| Hot Socketing | Supported |
5M80ZE64C4N Pin Configuration
| Pin 1 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 2 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 3 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 4 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 5 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 6 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 7 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 8 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 9 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 10 | GND β Ground reference |
| Pin 11 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 12 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 13 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 14 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 15 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 16 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 17 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 18 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 19 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 20 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 21 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 22 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 23 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 24 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 25 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 26 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 27 | GND β Ground reference |
| Pin 28 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 29 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 30 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 31 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 32 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 33 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 34 | TCK β JTAG test clock input (IEEE 1149.1) |
| Pin 35 | TMS β JTAG test mode select input |
| Pin 36 | TDI β JTAG test data input |
| Pin 37 | TDO β JTAG test data output |
| Pin 38 | GND β Ground reference |
| Pin 39 | VCCINT β Core supply voltage (1.8V) |
| Pin 40 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 41 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 42 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 43 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 44 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 45 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 46 | I/O β Dual-purpose user I/O pin (Bank 2) |
| Pin 47 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 48 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 49 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 50 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 51 | GND β Ground reference |
| Pin 52 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 53 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 54 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 55 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 56 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 57 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 58 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 59 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 60 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 61 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 62 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 63 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin 64 | I/O β Dual-purpose user I/O pin (Bank 1) |
| Pin EP | GND (Exposed Pad) β Thermal/ground pad; must be soldered to PCB ground plane |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M80ZE64C4N is suitable for 7 applications: I/O Expansion for Microcontrollers, Power Sequencing Controller for FPGAs and ASICs, Address Decoding and Chip-Select Logic, Bus Bridging and Protocol Translation, LED Driving and Industrial Display Control, Glue Logic in Industrial Automation, FPGA Configuration Supervisor.
I/O Expansion for Microcontrollers
The 5M80ZE64C4N serves as an instant-on I/O expander for microcontrollers that lack sufficient GPIO. With 79 user I/O pins and multi-voltage VCCIO banks (1.5V to 3.3V), it adds PWM outputs, keypad scanning, or sensor multiplexing to MCUs like the STM32 or PIC. The non-volatile flash configuration means the CPLD is active at power-on before the MCU initializes, providing fail-safe initial pin states. The 184 MHz fMAX enables sub-10 ns response to interrupt-driven events. Quartus Prime Lite free toolchain enables rapid prototyping without license costs.
Recommended
Power Sequencing Controller for FPGAs and ASICs
The 5M80ZE64C4N is widely used as a power-up and power-down sequencing controller for multi-rail FPGAs and ASICs requiring strict rail ordering. Its non-volatile instant-on behavior activates at system power-up and asserts enable signals to DC-DC converters in a defined sequence, then holds the FPGA in reset until all rails are stable. The CPLD's 2 global clocks and configurable output slew rates reduce EMI during sequencing events. Typical designs use 4 to 16 macro cells per sequence step, well within the 5M80's 64 LE capacity.
Recommended
Address Decoding and Chip-Select Logic
In microprocessor and DSP systems, the 5M80ZE64C4N implements high-speed address decoding and chip-select generation across multiple peripherals. With 79 available I/O and 184 MHz operation, it can decode 24-bit or wider address buses with sub-10 ns propagation delay, replacing dozens of discrete 74-series logic gates with a single reprogrammable device. The instant-on behavior means chip-selects are valid at power-on without waiting for MCU firmware to load, critical for systems with external boot memories.
Recommended
Bus Bridging and Protocol Translation
The 5M80ZE64C4N bridges between legacy parallel buses (ISA, SRAM, 8/16-bit MCU) and modern serial interfaces (SPI, I2C, UART). With multi-voltage I/O banks, it can simultaneously interface 5V-tolerant legacy devices and 1.8V modern ASICs. The on-chip 8 Kbit user flash stores configuration constants and lookup tables, eliminating external EEPROMs. Typical bridging applications include legacy-to-modern display controllers, sensor hub aggregation, and factory automation protocol converters.
Recommended
LED Driving and Industrial Display Control
The 5M80ZE64C4N drives multiplexed LED matrices, seven-segment displays, and character LCDs in industrial HMIs. Its 79 I/O pins support up to 8-digit 7-segment displays with current-driver enable signals. The 1.8V core and 3.3V VCCIO capability drive both modern LED drivers and legacy interfaces. The non-volatile flash storage retains display patterns and animations across power cycles. With 184 MHz fMAX, the CPLD refreshes displays with no visible flicker.
Recommended
Glue Logic in Industrial Automation
In factory automation and PLC systems, the 5M80ZE64C4N replaces discrete 74HC and 74LVC logic gates with a single programmable device, reducing board area and BOM cost. Functions include watchdog timer generation, signal conditioning, level shifting between field-bus voltages, and custom timing logic for motor control. The commercial temperature grade and surface-mount EQFP-64 package fit standard industrial PCB assembly processes. JTAG in-system programmability allows field updates without desoldering.
Recommended
FPGA Configuration Supervisor
The 5M80ZE64C4N supervises FPGA configuration from a parallel flash memory, monitoring the FPGA's CONF_DONE and nSTATUS signals and recovering from configuration errors by toggling nCONFIG. This offloads critical boot-time supervision from the system MCU, ensuring reliable FPGA startup even when the host processor is reset or being updated. The CPLD's instant-on behavior guarantees the FPGA boot supervisor is operational before any other system component powers up, a critical safety function in telecom and medical equipment.
Recommended
Recommended Products Summary
Engineering reference data for 5M80ZE64C4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M80ZE64C4/I5N | 5M80ZE64C4 | 5M80ZE64A5N | 5M160ZE64C4N | 5M160ZE64C5N | 5M40ZE64C4N |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 64-pin EQFP (E64) | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same | 64-pin EQFP (E64) - same |
| Logic Elements (Macro Cells) | 64 | 64 | 64 | 64 | 160 (+150%) | 160 (+150%) | 40 (-37.5%) |
| Speed Grade | C4 | I5 (industrial temp, C4 speed) | C4 | A5 (automotive) | C4 | C5 (slower) | C4 |
| Operating Temperature Grade | Commercial (0C to +85C) | Industrial (-40C to +100C) | Commercial | Automotive (-40C to +125C) | Commercial | Commercial | Commercial |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Maximum User I/O | 79 | 79 | 79 | 79 | 79 (same E64 package limits) | 79 | 79 |
| Configuration Memory | Non-volatile flash | Non-volatile flash | Non-volatile flash | Non-volatile flash | Non-volatile flash | Non-volatile flash | Non-volatile flash |
| Unit Price (qty 1, as of 2026-09-06) | $3.52 | [DATA_NEEDED: industrial grade premium] | ~$3.45 | [DATA_NEEDED: automotive grade premium] | ~$6.50 | ~$6.20 | ~$3.10 |
Key Differentiators
- Non-volatile flash configuration with instant-on (vs SRAM-based FPGAs (e.g., Cyclone IV))
- 79 user I/O pins in compact EQFP-64 package (vs 5M40ZE64C4N (same package))
- Multi-voltage VCCIO banks (1.5V/1.8V/2.5V/3.3V) (vs Single-voltage I/O CPLDs)
Design Notes
Decouple VCCINT (1.8V core) with at least one 0.1uF ceramic capacitor placed within 5 mm of the supply pin, plus a bulk 10uF tantalum or ceramic near the IC. Each VCCIO bank (VCCIO1, VCCIO2) requires its own 0.1uF decoupling cap even if both banks share the same voltage rail. The exposed pad (EP) must be soldered to a low-impedance ground plane to dissipate heat and provide electrical reference. Estimated: total decoupling requirement is approximately 3 to 5 capacitors; budget 100 nF + 10 uF per supply domain.
The EQFP-64 package has a 0.5 mm pitch and a large center exposed pad. Use microvia-in-pad PCB technology or a solder-mask-defined pad pattern to ensure reliable solder joint formation under the EP. Maximum reflow temperature per JEDEC J-STD-020 is 260C for 60 seconds peak. Maintain at least 0.2 mm keep-out between EP and inner signal traces to prevent solder wicking issues. The 0.5 mm pitch requires 4-mil trace and space design rules for fanout routing.
Pin 1 is identified by the dot marker on the top surface of the package. JTAG pins (TCK, TMS, TDI, TDO) must be routed with 4-mil traces kept short and away from switching signals to avoid programming errors. Both global clock inputs (CLK0, CLK1) should use matched-length routing if used for source-synchronous applications. The GND pins at positions 10, 27, 38, 51 form the recommended stitching pattern; connect each directly to the ground plane with short vias.
Do not leave unused I/O pins floating - enable the internal weak pull-up resistors in the Quartus Prime device configuration, or tie them externally to a valid logic level. The 5M80ZE64C4N does not support LVDS or HSTL I/O standards; only LVCMOS/LVTTL at 1.5V/1.8V/2.5V/3.3V are supported. The flash programming cycles are rated for at least 100 write/erase cycles - design the firmware update path to track and limit the number of field reprogramming events.
For outputs switching at 100 MHz or above, place a 33 ohm series damping resistor near the CPLD pin to reduce transmission-line ringing on traces longer than 25 mm. Enable slew-rate control (slow slew rate) in the Quartus Prime assignment editor for switching outputs to reduce EMI by approximately 6 to 10 dB at the cost of a small propagation delay increase. Estimated: 33 ohm damping reduces overshoot by approximately 50% on 50 mm microstrip traces.
Compliance Information
RoHS and lead-free compliant per Intel/Altera product page. Not AEC-Q100 qualified in this commercial speed grade - choose 5M80ZE64A5N variant for automotive applications.
