EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
MPN: EP1810LC-45 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $69.28 | $69.28 |
| 10 | $64.5 | $645.00 |
| 100 | $58.2 | $5,820.00 |
| 250 | $53.75 | $13,437.50 |
| 500 | $49.9 | $24,950.00 |
Drop-in alternatives for EP1810LC-45 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP1810LC-35
✅ Drop-In✓ In Stock
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View Datasheet →EP1810LC-25
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View Datasheet →EP1810LC-30
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View Datasheet →EP1810LC-20
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View Datasheet →EP1810JC-45
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View Datasheet →EP1810JC-35
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$5.48 / Unit
View Datasheet →EP1810JC-25
✅ Drop-In✓ In Stock
$6.8 / Unit
View Datasheet →EP1810LC-45 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 |
| Macro Cells | 48 |
| Maximum Inputs | 64 |
| Maximum Outputs | 48 |
| Logic Array Blocks | 4 |
| Propagation Delay (tpd) | 45 ns |
| Maximum Operating Frequency | 22.2 MHz |
| Supply Voltage (Vcc) | 5 V (±5%) |
| Process Technology | 5 V CMOS EPROM |
| Package | 68-pin PLCC (J-lead) |
| Operating Temperature | 0 °C to +70 °C (commercial) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
EP1810LC-45 Pin Configuration
| Pin 1 | I/O — Bidirectional macro cell I/O (pin 1) |
| Pin 2 | I/O — Bidirectional macro cell I/O (pin 2) |
| Pin 3 | I/O — Bidirectional macro cell I/O (pin 3) |
| Pin 4 | I/O — Bidirectional macro cell I/O (pin 4) |
| Pin 5 | I/O — Bidirectional macro cell I/O (pin 5) |
| Pin 6 | I/O — Bidirectional macro cell I/O (pin 6) |
| Pin 7 | I/O — Bidirectional macro cell I/O (pin 7) |
| Pin 8 | I/O — Bidirectional macro cell I/O (pin 8) |
| Pin 9 | I/O — Bidirectional macro cell I/O (pin 9) |
| Pin 10 | I/O — Bidirectional macro cell I/O (pin 10) |
| Pin 11 | I/O — Bidirectional macro cell I/O (pin 11) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Bidirectional macro cell I/O (pin 13) |
| Pin 14 | I/O — Bidirectional macro cell I/O (pin 14) |
| Pin 15 | I/O — Bidirectional macro cell I/O (pin 15) |
| Pin 16 | I/O — Bidirectional macro cell I/O (pin 16) |
| Pin 17 | I/O — Bidirectional macro cell I/O (pin 17) |
| Pin 18 | I/O — Bidirectional macro cell I/O (pin 18) |
| Pin 19 | I/O — Bidirectional macro cell I/O (pin 19) |
| Pin 20 | I/O — Bidirectional macro cell I/O (pin 20) |
| Pin 21 | I/O — Bidirectional macro cell I/O (pin 21) |
| Pin 22 | I/O — Bidirectional macro cell I/O (pin 22) |
| Pin 23 | I/O — Bidirectional macro cell I/O (pin 23) |
| Pin 24 | VCC — +5 V supply |
| Pin 25 | I/O — Bidirectional macro cell I/O (pin 25) |
| Pin 26 | I/O — Bidirectional macro cell I/O (pin 26) |
| Pin 27 | I/O — Bidirectional macro cell I/O (pin 27) |
| Pin 28 | I/O — Bidirectional macro cell I/O (pin 28) |
| Pin 29 | I/O — Bidirectional macro cell I/O (pin 29) |
| Pin 30 | I/O — Bidirectional macro cell I/O (pin 30) |
| Pin 31 | I/O — Bidirectional macro cell I/O (pin 31) |
| Pin 32 | I/O — Bidirectional macro cell I/O (pin 32) |
| Pin 33 | I/O — Bidirectional macro cell I/O (pin 33) |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — Bidirectional macro cell I/O (pin 35) |
| Pin 36 | I/O — Bidirectional macro cell I/O (pin 36) |
| Pin 37 | I/O — Bidirectional macro cell I/O (pin 37) |
| Pin 38 | I/O — Bidirectional macro cell I/O (pin 38) |
| Pin 39 | I/O — Bidirectional macro cell I/O (pin 39) |
| Pin 40 | I/O — Bidirectional macro cell I/O (pin 40) |
| Pin 41 | I/O — Bidirectional macro cell I/O (pin 41) |
| Pin 42 | I/O — Bidirectional macro cell I/O (pin 42) |
| Pin 43 | I/O — Bidirectional macro cell I/O (pin 43) |
| Pin 44 | I/O — Bidirectional macro cell I/O (pin 44) |
| Pin 45 | GND — Ground |
| Pin 46 | I/O — Bidirectional macro cell I/O (pin 46) |
| Pin 47 | I/O — Bidirectional macro cell I/O (pin 47) |
| Pin 48 | I/O — Bidirectional macro cell I/O (pin 48) |
| Pin 49 | I/O — Bidirectional macro cell I/O (pin 49) |
| Pin 50 | I/O — Bidirectional macro cell I/O (pin 50) |
| Pin 51 | I/O — Bidirectional macro cell I/O (pin 51) |
| Pin 52 | I/O — Bidirectional macro cell I/O (pin 52) |
| Pin 53 | I/O — Bidirectional macro cell I/O (pin 53) |
| Pin 54 | I/O — Bidirectional macro cell I/O (pin 54) |
| Pin 55 | I/O — Bidirectional macro cell I/O (pin 55) |
| Pin 56 | GND — Ground |
| Pin 57 | I/O — Bidirectional macro cell I/O (pin 57) |
| Pin 58 | I/O — Bidirectional macro cell I/O (pin 58) |
| Pin 59 | I/O — Bidirectional macro cell I/O (pin 59) |
| Pin 60 | I/O — Bidirectional macro cell I/O (pin 60) |
| Pin 61 | I/O — Bidirectional macro cell I/O (pin 61) |
| Pin 62 | I/O — Bidirectional macro cell I/O (pin 62) |
| Pin 63 | I/O — Bidirectional macro cell I/O (pin 63) |
| Pin 64 | I/O — Bidirectional macro cell I/O (pin 64) |
| Pin 65 | I/O — Bidirectional macro cell I/O (pin 65) |
| Pin 66 | I/O — Bidirectional macro cell I/O (pin 66) |
| Pin 67 | I/O — Bidirectional macro cell I/O (pin 67) |
| Pin 68 | VCC — +5 V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1810LC-45 is suitable for 6 applications: Legacy Industrial PLC Bus-Interface Glue Logic, MIL-STD-883 Aerospace Avionics Subsystems, Telecom Backplane Address Decoder and Protocol Bridge, Vintage Workstation Peripheral Controller, Test Equipment Custom Pattern Generator, Medical Imaging Front-End Interface.
Legacy Industrial PLC Bus-Interface Glue Logic
The EP1810LC-45 fits legacy 5 V PLC backplane designs because it integrates up to 64 inputs and 48 outputs of combinatorial and registered logic into one 68-pin PLCC device, replacing 4-6 discrete 74LS245/74LS244/74LS138 buffers and decoders. Its 45 ns propagation delay comfortably supports classic 8/16-bit industrial bus cycles (e.g., ISA, PC/104, VME) running below 22 MHz, while the 5 V CMOS EPROM process ensures >10 year data retention in unheated control cabinets. Designers using the EP1810LC-45 in PLC retrofit boards place it on a PLCC socket for easy UV-erase and field reprogramming during commissioning.
Recommended
MIL-STD-883 Aerospace Avionics Subsystems
The EP1810LC-45's 5 V CMOS EPROM process provides excellent single-event-upset tolerance and radiation hardness, which is why it remains qualified for MIL-STD-883 avionics subsystems and legacy military controllers. The 68-pin PLCC ceramic windowed package supports in-system UV erasure during avionics software updates, and the 900-gate / 48-macro-cell capacity is well-matched to flight-control state machines and weapon-system interface logic. Engineers pair the EP1810LC-45 with MIL-graded 54LS TTL peripherals and qualify the assembly to the target platform's environmental stress screening profile.
Recommended
Telecom Backplane Address Decoder and Protocol Bridge
In vintage telecom shelves (e.g., TDM cross-connects, SONET mux cards from the late 1990s), the EP1810LC-45 served as the central address decoder and protocol-bridge device, accepting parallel bus addresses and generating chip-select, interrupt, and timing-control signals for surrounding framers and transcoders. The 64-input limit accommodates wide address buses plus auxiliary control lines, while 48 outputs drive an entire backplane's worth of selects. The 5 V supply and 45 ns tpd are still compatible with H.110 CT-bus timing and classic HDLC controllers, making the EP1810LC-45 a faithful long-term replacement.
Recommended
Vintage Workstation Peripheral Controller
The EP1810LC-45 was widely designed into Sun, HP, and DEC workstation peripheral controllers of the early 1990s as a state-machine engine driving SCSI, parallel-port, and graphics-accelerator glue logic. The 48 macro cells are sufficient to encode the entire SCSI arbitration/state machine plus parallel-port handshaking in a single device, replacing a board full of 22V10 PALs. The PLCC socket also allowed field technicians to swap programmed devices when upgrading I/O firmware. For modern restoration projects, the EP1810LC-45 is a like-for-like replacement that preserves the original 5 V signaling levels.
Recommended
Test Equipment Custom Pattern Generator
Test-and-measurement equipment (logic-analyzer pods, in-circuit tester fixtures, custom ATE) often uses the EP1810LC-45 as a programmable pattern generator because its 48 macro cells can hold 48 bits of stimulus pattern per clock and the 45 ns tpd allows generation of stimulus edges up to ~22 MHz. The PLCC socket allows engineers to swap patterns between test runs without re-soldering, and the UV-erasable window supports rapid iteration during test-program development. The 5 V CMOS outputs can drive 50 Ω controlled-impedance test fixtures directly when buffered.
Recommended
Medical Imaging Front-End Interface
Long-lifecycle medical imaging platforms (CT, MRI, and ultrasound front-ends certified in the late 1990s and 2000s) often contain EP1810LC-45 devices timing the analog front-end multiplexers and ADC sample/hold control lines. The deterministic 45 ns propagation delay is critical for aligning ADC acquisition windows with ultrasound transmit bursts, and the 48 outputs can fan out to multiple analog channels simultaneously. Because re-certifying a medical device platform costs millions, hospitals and OEMs maintain spare EP1810LC-45 stock from Rochester Electronics to keep these certified systems in service.
Recommended
Recommended Products Summary
Engineering reference data for EP1810LC-45 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1810LC-35 | EP1810LC-25 | EP1810JC-45 |
|---|---|---|---|---|
| Brand | Rochester Electronics (formerly Altera/Intel) | Rochester Electronics (formerly Altera) | Rochester Electronics (formerly Altera) | Rochester Electronics (formerly Altera) |
| Package | 68-pin PLCC (J-lead) - same | 68-pin PLCC (J-lead) - same | 68-pin PLCC (J-lead) - same | 68-pin PLCC (J-lead) - same |
| Family | Altera Classic EPLD | Altera Classic EPLD - same | Altera Classic EPLD - same | Altera Classic EPLD - same |
| Propagation Delay (tpd) | 45 ns | 35 ns (-22%) | 25 ns (-44%) | 45 ns (same) |
| Maximum Frequency | 22.2 MHz | ~28.5 MHz | ~40 MHz | 22.2 MHz (same) |
| Usable Gates | 900 | 900 (same) | 900 (same) | 900 (same) |
| Macro Cells | 48 | 48 (same) | 48 (same) | 48 (same) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) |
| Package Type | Ceramic windowed (erasable) | Ceramic windowed (same) | Ceramic windowed (same) | Plastic (one-time-programmable) |
| Lifecycle Status | Obsolete (Rochester last-time-buy) | Obsolete (Rochester last-time-buy) | Obsolete (Rochester last-time-buy) | Obsolete (Rochester last-time-buy) |
Key Differentiators
- Drop-in compatible with entire EP1810LC speed-grade family (vs EP1810LC-35)
- Plastic-package field-replacement variant available (vs EP1810JC-45)
- MIL-STD-883 screened variant for defense programs (vs EP1810GM883B)
- Authorized long-term supply through Rochester Electronics (vs Generic/independent-distributor stock)
Design Notes
The EP1810LC-45 requires a tightly regulated 5 V ±5% supply (4.75 V to 5.25 V). Place a 100 nF X7R ceramic decoupling capacitor within 5 mm of each VCC pin (pins 24 and 68) and a bulk 10 µF tantalum or aluminum polymer capacitor on the same 5 V rail. The device draws up to ~200 mA ICC during AC switching activity; ensure the regulator provides at least 400 mA headroom. Estimated: at 22.2 MHz toggle rate with all 48 outputs switching into 50 pF loads, average ICC may rise to ~150 mA; verify with the original Altera Classic EPLD family datasheet ICC vs frequency curves.
Use a machined-pin PLCC-68 socket (e.g., 3M Textool or equivalent) for development to allow UV-erase and reprogram cycles; for production, socket only if field updates are required. Keep all I/O traces shorter than 50 mm to avoid transmission-line reflections; place 33 Ω series damping resistors near the EP1810LC-45 outputs if driving capacitive loads >50 pF. Connect all four GND pins (12, 34, 45, 56) directly to a ground plane with short, wide traces - the part relies on these for TTL-output drive strength.
Do not assume a '45' suffix speed grade means 'any 45 ns part is acceptable' - verify against the full Altera Classic EPLD family datasheet because some second-source variants have different output drive strengths. The PLCC-68 footprint is also used by 68-pin microcontrollers (e.g., early 8051 derivatives); double-check the pin-1 chamfer orientation before soldering, because reverse insertion will destroy the device. Lastly, Rochester-sourced parts may ship without the original Altera anti-static tube; confirm ESD handling procedures (≥1 kV HBM) before board-level assembly.
Route the 5 V power trace to both VCC pins (24 and 68) in a star topology from the regulator output rather than daisy-chaining through other logic devices; this minimizes VCC droop during simultaneous output switching. Keep the oscillator or clock-input trace (any user-assigned I/O pin serving as clock) away from high-di/dt outputs and surround it with ground guard traces on both sides. Maintain a continuous ground plane under the entire PLCC-68 footprint; the four GND pins (12, 34, 45, 56) should each have at least two ground vias for low-impedance return paths.
Compliance Information
The EP1810LC-45 was originally released by Altera (now Intel) before modern RoHS/REACH compliance mandates; current Rochester-sourced inventory may be supplied with original-era lead finish. Request a Certificate of Compliance from Rochester Electronics for current RoHS/REACH status before using in RoHS-restricted regions (EU, California). The part is not AEC-Q100 qualified (commercial 0-70 °C only); for automotive use, choose an automotive-grade MAX 3000A or MAX II CPLD instead.
